2D Semiconductor Channel With Nanoparticles for Low-Resistance Scaling
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Solution Overview
Problem
Existing semiconductor devices face limitations in reducing size due to performance degradation issues, such as increased contact resistance and decreased mobility, especially when channel thickness decreases.
Innovation Solution
A semiconductor device utilizing a two-dimensional semiconductor material with selectively deposited metallic nanoparticles on defects and grain boundaries, improving electrical conductivity and reducing short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of semiconductor devices is reduced, then more devices can be integrated and driving speed increases, but performance degradation occurs due to increased contact resistance and decreased mobility
Solution Approach 1:
The patent changes the material parameter from traditional silicon to two-dimensional materials (such as MoS2, WS2, MoSe2, WSe2, NbSe2, ReSe2, black phosphorus, or graphene) with specific bandgap ranges (0.1-3.0 eV for semiconductors, 0 eV for metals). This material parameter change enables maintaining high mobility and low contact resistance even at reduced device sizes, resolving the performance degradation issue while achieving higher integration density
Solution Approach 2:
The patent employs composite structures combining two-dimensional semiconductor materials with metallic nanoparticles or metal layers. The two-dimensional material layer (1-10 layers) provides the channel with high mobility, while the metallic nanoparticles (Ru, RuO, Mo, W, Co, TiN, Ti, or Al) deposited on defects and grain boundaries provide excellent electrical contact, creating a composite system that overcomes the limitations of single-material devices at scaled dimensions
2Length of moving object
If two-dimensional semiconductor materials are used, then device size can be reduced with maintained performance, but manufacturing complexity increases due to selective deposition processes
Solution Approach 1:
The patent utilizes self-service mechanisms where metallic nanoparticles automatically deposit on defect sites and grain boundaries of the two-dimensional material layer without requiring complex lithographic patterning. The nanoparticles selectively bind to high-energy sites (defects, grain boundaries, dislocations) through surface energy minimization, enabling automated defect passivation and simplifying the manufacturing process while maintaining reduced device dimensions
Solution Approach 2:
The patent introduces metallic nanoparticles as intermediary elements that mediate between the two-dimensional semiconductor channel and the source/drain electrodes. These nanoparticles serve as intermediate contact layers that reduce contact resistance and passivate defects, simplifying the overall device structure and fabrication process while enabling scaled-down dimensions
3Reliability
If metallic nanoparticles are deposited on two-dimensional material layer, then electrical conductivity improves and contact resistance decreases, but device structure becomes more complex
Solution Approach 1:
The patent extracts and addresses only the critical defect sites and grain boundaries within the two-dimensional material layer by selectively depositing metallic nanoparticles on these specific locations. Rather than uniformly modifying the entire layer, the nanoparticles are targeted to high-impact defect regions, minimizing structural complexity while maximizing electrical conductivity improvement and contact resistance reduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor device achieves enhanced performance with reduced size, improved on-current, and controlled channel polarity, threshold voltage, and off-current, overcoming limitations of traditional silicon-based devices.
Implementation Method 1
metallic nanoparticles selectively deposited on defects and grain boundaries of the two-dimensional material layer
Data Source
Figure 1
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AI summary
A semiconductor device may include a two-dimensional material layer including a two-dimensional semiconductor material having a polycrystalline structure; metallic nanoparticles partially on the two-dimensional material layer; a source electrode and a drain electrode respectively on both sides of the two-dimensional material layer; and a gate insulating layer and a gate electrode on the two-dimensional material layer between the source electrode and the drain electrode.