2D CMOS Nanosheet Channel Stack for Spacer Damage Resistance
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Solution Overview
Problem
Nanosheet technology in CMOS scaling faces issues as devices become smaller and closer together, leading to interference and damage during the formation of inner spacers.
Innovation Solution
Utilizing multiple 2D channel layers comprising a bottom, core, and top layer of different 2D channel materials to increase thickness and prevent damage during spacer formation, with the bottom and top layers being PFET doped and the core layer being NFET doped, enhancing junction and contact quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If nanosheet devices are scaled down to be smaller and closer together, then device density and integration are improved, but interference between devices increases and damage during spacer formation occurs
Solution Approach 1:
The channel is segmented into multiple thin 2D material layers (bottom layer, core layer, top layer) instead of using a single thick nanosheet. This segmentation allows the channel to maintain mechanical flexibility and resist damage during spacer formation while enabling closer device spacing for higher density.
Solution Approach 2:
The patent uses composite 2D material structures with different materials for different layers (e.g., MoS2 for bottom and top layers, WS2 for core layer). This composite approach optimizes both mechanical strength to prevent damage during processing and electrical performance for high-density device operation.
2Ease of manufacture
If single-layer nanosheets are used, then manufacturing is simpler, but the channel is too thin and susceptible to damage during spacer formation
Solution Approach 1:
The channel is divided into multiple thin 2D material layers (bottom layer, core layer, top layer) instead of using a single thick nanosheet. This segmentation allows the channel to maintain mechanical flexibility and resist damage during spacer formation while enabling closer device spacing for higher density.
Solution Approach 2:
Different 2D materials are used for different layers based on their specific properties - MoS2 for bottom and top layers providing mechanical strength, WS2 for core layer providing electrical performance. This local optimization ensures both robustness during manufacturing and performance in operation.
3Manufacturing precision
If thicker channels are used to prevent damage, then process margin is improved, but device scaling and integration are compromised
Solution Approach 1:
The channel is segmented into multiple thin 2D material layers (bottom layer, core layer, top layer) instead of using a single thick nanosheet. This segmentation allows the channel to maintain mechanical flexibility and resist damage during spacer formation while enabling closer device spacing for higher density.
Solution Approach 2:
Instead of increasing thickness in the vertical dimension, the patent uses multiple ultra-thin layers stacked vertically, each only a few nanometers thick. This approach provides the necessary mechanical robustness through cumulative thickness while maintaining the ultra-thin profile needed for scaled device integration.
Data Source
AI summary
A microelectronic structure that includes a nanosheet FET that includes a plurality of channel layers. Each of the plurality of channel layers includes a bottom layer, a core layer, and a top layer. The bottom layer and the top layer are comprised of a first 2D channel material and the core layer is comprised of a second 2D channel material. The first 2D channel material and the second 2D channel material are different.