2D Material Contact Structure for Low-Resistance Transistor Wiring

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Solution Overview

Problem

The miniaturization of semiconductor devices is limited due to the decrease in charge mobility and the occurrence of short-channel effects in three-dimensional bulk materials, and performance degradation caused by contact resistance between two-dimensional (2D) materials and other components in transistors using 2D materials as channels.

Innovation Solution

A 2D material-based wiring conductive layer contact structure is introduced, comprising a semiconducting 2D material wiring, a conductive layer, and a metallic 2D material layer between them, which reduces contact resistance by using materials like transition metal dichalcogenides or black phosphorene for the wiring and metallic 2D materials that exhibit metallicity, semi-metallicity, or superconductivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If three-dimensional bulk material is used for semiconductor device miniaturization, then device size can be reduced, but charge mobility decreases and short-channel effects occur

Engineering Contradiction:
Improvedevice sizeVSAvoidcharge mobility
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The patent transitions from three-dimensional bulk material to two-dimensional material, fundamentally changing the dimensional parameter of the semiconductor channel. This parameter change enables continued device miniaturization while maintaining high charge mobility, as 2D materials preserve their electrical transport properties even at atomic thickness scales, avoiding the short-channel effects that plague scaled 3D devices

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The invention explicitly moves from 3D bulk material to 2D material for the channel layer, utilizing the additional dimensional constraint to achieve superior electrical properties. The 2D structure provides enhanced carrier mobility and reduced scattering effects, allowing smaller device dimensions without sacrificing performance

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If two-dimensional material is used as channel in transistor, then charge mobility is maintained and short-channel effect is reduced, but contact resistance between 2D material and other components increases

Engineering Contradiction:
Improvecharge mobilityVSAvoidcontact resistance
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an intermediary layer or modified contact structure between the 2D material channel and the metal electrodes. This intermediary interface reduces the contact resistance by improving the coupling between the 2D material and the three-dimensional electrode, while preserving the high mobility benefits of the 2D channel material

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention applies local quality modification at the contact region between the 2D material and metal electrode. By tailoring the interface properties locally (such as using doping, dipole layers, or specific contact geometries), the contact resistance is reduced without affecting the bulk properties and high mobility of the 2D channel material

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12142697B2Two-dimensional material-based wiring conductive layer contact structures, electronic devices including the same, and methods of manufacturing the electronic devices
Publication Date: 2024.11.12 SAMSUNG ELECTRONICS CO LTD
  • US12142697B2 patent drawing
  • US12142697B2 patent drawing
  • US12142697B2 patent drawing

AI summary

Provided are two-dimensional material (2D)-based wiring conductive layer contact structures, electronic devices including the same, and methods of manufacturing the electronic devices. A 2D material-based field effect transistor includes a substrate; first to third 2D material layers on the substrate; an insulating layer on the first 2D material layer; a source electrode on the second 2D material layer; a drain electrode on the third 2D material layer; and a gate electrode on the insulating layer. The first 2D material layer is configured to exhibit semiconductor characteristics, and the second and third 2D material layers are metallic 2D material layers. The first 2D material layer may include a first channel layer of a 2D material and a second channel layer of a 2D material. The first 2D material layer may partially overlap the second and third 2D material layers.