2D Data Error Correction in Multi-Chip Memory Systems
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Solution Overview
Problem
As memory devices become more densely integrated and smaller in size, errors such as reading or writing incorrect data become more likely, and existing error correction techniques often consume too much memory space, necessitating a method to improve error correction efficiency.
Innovation Solution
A memory device and system that uses a method involving multiple RAM chips, where a memory controller generates two-dimensional data by combining data from multiple storage regions, performs error detection and correction using SEC-DED operations, and reconstructs data to process errors effectively, reducing operational latency and memory overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction techniques are used to correct reading or writing errors, then reliability is improved, but memory space is consumed excessively
Solution Approach 1:
The patent transitions from traditional one-dimensional error correction to two-dimensional error correction by organizing data from multiple RAM chips into a 2D matrix structure. This dimensional change enables more efficient error detection and correction algorithms that can identify and correct errors with less overhead compared to conventional 1D approaches, thereby improving reliability while consuming less memory space.
Solution Approach 2:
The patent divides the memory system into multiple segmented RAM chips, each storing a portion of the data. By segmenting the data across multiple chips and organizing it in a 2D structure, the system can apply error correction to specific segments rather than the entire memory space, reducing the overall overhead required for error correction while maintaining reliability.
2Reliability
If data is read from multiple RAM chips and combined into 2D data, then error correction efficiency is improved, but operational complexity increases
Solution Approach 1:
The patent creates a universal 2D data structure that can handle various error scenarios (single errors, double errors, etc.) through a unified error correction framework. This multi-functional approach allows the same 2D structure and correction algorithms to address different types of errors, simplifying the operational complexity despite reading from multiple chips, as the system uses a consistent methodology rather than separate procedures for each error type.
Data Source
AI summary
Provided are a memory device, a memory system, and a method of operating the memory device. A method of operating a memory device including a plurality of random access memory (RAM) chips includes inputting a read command, reading a plurality of pieces of block data including first block data corresponding to the read command from each of the plurality of RAM chips, generating two-dimensional (2D) data by combining the plurality of pieces of block data read from each of the RAM chips, and processing the read command by using the 2D data.