Two-Dimensional Error Correction for Flash Memory Blocks
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Solution Overview
Problem
NAND Flash Memory faces challenges such as high cost, slow sequential write time, limited endurance, and data retention issues due to aggressive scaling, which are exacerbated by the need for higher-density cells that compromise reliability and endurance.
Innovation Solution
Implementing two independent error correcting codes, one at the page level (horizontal) and another across all pages in a block (vertical), to enhance data recovery and reliability, allowing for increased endurance and data retention, or reduced costs by using higher-density Flash memory without compromising reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If higher-density Flash memory is used to reduce cost, then cost is reduced, but endurance and data retention deteriorate
Solution Approach 1:
The patent transitions from traditional single-direction error correction to two-dimensional error correction by adding a vertical coding dimension across multiple pages. This dimensional expansion allows the system to correct errors that would be unrecoverable in single-page coding, thereby improving reliability of higher-density Flash memory without increasing cost.
2Productivity
If conventional single-page error correction is used, then decoding can be done during read operations without additional reads, but read reliability deteriorates with aggressive scaling
Solution Approach 1:
The patent segments the error correction process into two independent dimensions: horizontal error correction for individual pages and vertical error correction across multiple pages. This segmentation allows the system to maintain the efficiency of page-level decoding while adding cross-page error correction capability to handle scaling-induced errors.
Solution Approach 2:
The patent introduces a vertical coding dimension that operates across multiple pages in addition to the traditional horizontal page-level coding. This two-dimensional approach enables error correction for bits that fail within individual pages, significantly improving read reliability without sacrificing decoding efficiency.
3Reliability
If more powerful error correction codes are used to handle bit errors, then read reliability is improved, but power efficiency and throughput deteriorate
Solution Approach 1:
The patent implements partial error correction by first attempting horizontal decoding for each page, and only invoking vertical decoding when horizontal decoding fails. This partial approach corrects the most common error types efficiently while providing a safety net for more difficult error patterns, thereby improving reliability without proportionally increasing power consumption and throughput overhead.
Data Source
AI summary
Method for encoding information in a flash memory block which combines an independent encoding of each page with a block-level code across multiple pages. The method includes two independent error correction codes, one in horizontal direction and one in vertical direction, with horizontal direction error correction decoding; and vertical direction erasure correction decoding.