2D Execution Lane Array for Versatile Image Processing

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Solution Overview

Problem

Traditional image processing technologies face a tradeoff between energy efficiency and versatility, with software-based processors consuming more energy due to finer grained data structures and custom hardware processors being limited in application flexibility.

Innovation Solution

A technology platform featuring a two-dimensional execution lane array and a two-dimensional shift register, enabling a versatile application software development environment that processes larger blocks of data efficiently while allowing for a wide range of image processing tasks, including kernels for convolutions, denoising, and Fourier transformations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If software-based general purpose processors are used for image processing, then versatility and application software development capability are improved, but energy consumption per unit of data increases

Engineering Contradiction:

Improveapplication software development capabilityVSAvoidenergy consumption per unit of data

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The processor is segmented into multiple execution lanes (e.g., 16x16 array) that can operate independently and in parallel. Each lane can be configured for different operations, allowing the system to process different data types and operations simultaneously, thus maintaining versatility while improving energy efficiency through parallel specialized processing.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The execution lanes are dynamically configurable through a programming model that allows runtime reconfiguration of lane behavior. The system can switch between different processing modes (e.g., integer operations, floating point operations, different data types) without hardware changes, maintaining adaptability while optimizing for specific tasks to reduce energy consumption.

Inventive Principle:

Principle #15Dynamics

2Use of energy by moving object

If custom designed fixed function circuitry is used for image processing, then power consumption per unit of data is reduced, but the set of performable tasks becomes limited

Engineering Contradiction:

Improvepower consumption per unit of dataVSAvoidset of performable tasks

Core Design Contradiction:

Use of energy by moving objectVSAdaptability or versatility

Solution Approach 1:

Each execution lane is designed as a universal processing unit that can perform multiple operations (arithmetic, logical, memory access) depending on configuration. The same hardware structure can be programmed to execute different algorithms and process different data types, providing fixed-function efficiency for each specific task while maintaining overall system versatility.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system changes operational parameters (data types, operation modes, lane configurations) through software programming rather than hardware modification. This allows the fixed-function circuitry to be reconfigured for different tasks by changing control parameters, maintaining energy efficiency while expanding the range of performable tasks.

Inventive Principle:

Principle #35Parameter changes

3Use of energy by moving object

If larger blocks of data are processed using custom circuits, then power consumption per unit of data is reduced, but flexibility in processing different data types is lost

Engineering Contradiction:

Improvepower consumption per unit of dataVSAvoidflexibility in processing different data types

Core Design Contradiction:

Use of energy by moving objectVSAdaptability or versatility

Solution Approach 1:

A programming model and control layer act as intermediaries between the software and the execution lanes. This intermediary translates high-level programming instructions into configurations that optimize data block processing, allowing the system to process larger data blocks efficiently while maintaining the ability to handle different data types through software-controlled parameter adjustment.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentEP3479341B1Core processes for block operations on an image processor having a two-dimensional execution lane array and a two-dimensional shift register

Publication Date: 2023.11.29 GOOGLE LLC

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AI summary

A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, doubling a simultaneous shift amount of multiple rows or columns of the two dimensional shift register array with each next iteration. The method also includes executing one or more instructions within respective lanes of the two dimensional execution lane array in between shifts of iterations. Another method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly executing one or more instructions within respective lanes of the execution lane array that select between content in different registers of a same array location in between repeated simultaneous shifts of multiple rows or columns of data in the two dimensional shift register array.