2D Ferroelectric FinFET Gate Stack for Steep Subthreshold Swing
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Solution Overview
Problem
Current methods of fabricating field effect transistors (FET) devices face challenges in controlling layer thickness and interface composition with atomic precision, leading to limitations in subthreshold swing and transistor power dissipation due to physical limitations.
Innovation Solution
A method for fabricating semiconductor devices involves forming a fin structure on a substrate, followed by a passivation layer, a channel layer, a dielectric layer, and a cap layer, with an annealing process to transform the dielectric layer into a ferroelectric layer, and integrating a gate stack with a gate-first process, utilizing 2D materials and ferroelectric dielectrics to achieve precise control and low thermal budget.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional FET fabrication methods are used, then manufacturing process is simpler, but layer thickness and interface composition cannot be controlled with atomic precision
Solution Approach 1:
The fabrication process is divided into discrete atomic layers deposited sequentially, with each layer's thickness precisely controlled at the atomic level. This segmentation enables atomic precision control of layer thickness while maintaining a systematic manufacturing approach.
Solution Approach 2:
The patent employs atomic layer deposition (ALD) technology that deposits materials one atomic layer at a time, fundamentally changing the deposition parameter from continuous thickness control to discrete atomic-level control. This enables precise thickness control without proportionally increasing process complexity.
2Manufacturing precision
If conventional FET fabrication methods are used, then manufacturing process is simpler, but interface composition cannot be controlled with atomic precision
Solution Approach 1:
The interface composition is controlled by segmenting the deposition process into distinct atomic layers, where each layer's composition is precisely defined and deposited sequentially. This enables atomic precision control of interface composition between different materials.
Solution Approach 2:
The patent uses ALD to change the deposition parameter from bulk material deposition to atomic-layer precision deposition, enabling precise control of interface composition. The process allows different materials to be deposited in controlled atomic layers with well-defined interfaces.
3Loss of energy
If physical limitation of 60 mV/decade is accepted, then subthreshold swing is limited, but transistor power dissipation cannot be downscaled
Solution Approach 1:
The patent changes the physical parameters of the transistor structure by implementing atomically precise thin film layers and controlled interface compositions. This enables sub-60mV/decade subthreshold swing characteristics, allowing steep switching and reduced power dissipation without sacrificing ease of operation.
Solution Approach 2:
The patent employs composite material structures with multiple atomic layers of different materials (e.g., high-k dielectrics, metal gates, channel materials) with precisely controlled interfaces. This composite structure enables improved electrical characteristics including steep subthreshold swing and reduced power dissipation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables improved device properties and uniformity across the wafer, allowing for lower voltage operation and reduced power dissipation, achieving steep subthreshold swing and enabling low power operation.
Implementation Method 1
an annealing process to transform the dielectric layer into a ferroelectric layer
Data Source
AI summary
A semiconductor device includes a fin structure, a two-dimensional (2D) material channel layer, a ferroelectric layer, and a metal layer. The fin structure extends from a substrate. The 2D material channel layer wraps around at least three sides of the fin structure. The ferroelectric layer wraps around at least three sides of the 2D material channel layer. The metal layer wraps around at least three sides of the ferroelectric layer.