2D Material FET Bi-Layer Source Drain Parasitic Resistance
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Solution Overview
Problem
Current semiconductor device formation using nanosheet stacks is limited by gate-to-gate pinch off and short channel effects, which restricts device scaling beyond 40 nm gate pitch and degrades electrostatic control due to quantum confinement effects, while 2D materials face high parasitic resistance issues with thin channels.
Innovation Solution
A field-effect transistor (FET) device is developed using a 2D material channel with a bi-layer metal source/drain and a high-k gate dielectric extending under the sidewall spacer, reducing parasitic resistance and improving electrostatic control by enhancing carrier generation and reducing external resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If nanosheet stacks are used for device formation, then device scaling is achieved, but gate-to-gate pinch off and short channel effects occur which degrade electrostatic control
Solution Approach 1:
The patent changes the channel material from conventional nanosheet silicon to two-dimensional materials (such as MoS2, WS2, WSe2) which fundamentally alter the electrostatic properties. This material parameter change enables better electrostatic control at scaled dimensions by eliminating quantum confinement effects while maintaining thin channel characteristics for improved gate control.
Solution Approach 2:
The patent employs a composite structure combining two-dimensional material channels with high-k gate dielectric materials. This composite approach leverages the unique properties of 2D materials (atomically thin, high mobility) combined with high-k dielectrics (superior electrostatic control) to achieve both scaling and improved electrostatic performance simultaneously.
2Reliability
If 2D materials are used for thin channels, then electrostatic control is improved, but parasitic resistance increases
Solution Approach 1:
The patent applies local quality by using a bi-layer metal source/drain structure where different metal layers serve different functions: the first metal layer (e.g., TiN, TaN) provides low contact resistance with the 2D channel material, while the second metal layer (e.g., Cu, Al, W) provides low bulk resistance for current transport. This localized optimization of material properties at different positions (contact interface vs. bulk) simultaneously addresses both contact resistance and bulk resistance components of parasitic resistance.
Solution Approach 2:
The bi-layer metal source/drain structure is a composite material solution combining two different metal materials. The first metal layer is selected for its compatibility and low contact resistance with 2D materials, while the second metal layer is selected for its excellent electrical conductivity. This composite structure enables the source/drain to overcome the high parasitic resistance issue inherent in single-material designs.
Data Source
AI summary
An approach to forming a field-effect transistor device formed with a two-dimensional material. The field-effect transistor device includes a channel composed of the two-dimensional material on a substrate and a high-k gate dielectric on the channel and extending under a sidewall spacer and around the sidewall spacer. The field-effect transistor includes a metal gate that is inside the high-k gate dielectric and over the channel. The source/drain is on a portion the two-dimensional material on the substrate. The source/drain abuts the sidewall spacer and is composed of a bi-layer metal.