2D FET On-Chip Thin Film Deposition Characterization
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Solution Overview
Problem
Existing integrated circuits with transistors are not designed to operate effectively in liquid environments and lack the capability for on-chip electrical characterization of thin film layer deposition parameters such as thickness and porosity, relying on off-chip optical methods which are complex and costly.
Innovation Solution
An integrated circuit with 2D field-effect transistors and on-chip thin film layer deposition that includes environmentally non-reactive electrodes for voltage application and measurement, allowing for electrical characterization of thin film layers directly on the chip using liquid-mediated deposition and voltage-assisted techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If off-chip optical methods are used for characterizing thin film layers, then measurement capability is provided, but device complexity and cost increase
Solution Approach 1:
The patent combines the thin film deposition system and electrical characterization system into a single integrated chip. The FET array is fabricated with integrated electrodes and deposition chambers, allowing both deposition and electrical measurement to occur on the same device without requiring separate off-chip optical characterization equipment.
Solution Approach 2:
The FET array serves multiple functions: it acts as both the deposition substrate for thin film layers and the measurement device for characterizing those layers. The same electrodes used for electrical operation are also used for electrical characterization of the deposited films, eliminating the need for separate characterization equipment.
2Adaptability or versatility
If transistors are designed to work in liquid environments, then biosensing capability is improved, but operating speed decreases
Solution Approach 1:
The patent applies different quality requirements to different parts of the system. The gate area is designed for liquid environment interaction with slow response times acceptable for chemical equilibrium measurements, while the source and drain regions maintain fast electrical response characteristics for rapid signal detection and processing.
Solution Approach 2:
The system dynamically adapts its operating mode based on the measurement requirements. During deposition phases, the transistor operates in a regime optimized for material accumulation, while during sensing phases, it switches to a regime optimized for rapid electrical response, balancing liquid compatibility and speed.
3Productivity
If electrical characterization is performed on-chip, then productivity and cost-effectiveness improve, but measurement precision requirements increase
Solution Approach 1:
The FET array performs self-characterization by using its own electrical response to the deposited thin film layers as the measurement signal. The change in electrical properties (such as threshold voltage shift or conductance change) directly reflects the deposition characteristics, allowing the device to characterize itself without external measurement equipment.
Solution Approach 2:
The system uses real-time electrical feedback from the FET array during deposition to monitor and control thin film layer formation. The electrical measurements provide immediate feedback on deposition progress, enabling precise control of film thickness and properties while maintaining high productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables real-time, cost-effective electrical characterization and control of thin film layer deposition on integrated circuits, enhancing the reliability and sensitivity of biosensors by directly measuring thickness and porosity on-chip, reducing the need for complex off-chip methods.
Implementation Method 1
at least one environmentally non-reactive electrode is configured to impart a counter electrode voltage (VCE) to a liquid received in a gate area such that the counter electrode voltage imparted to the liquid provides a gate voltage for the FETs in the array covered by the liquid
Implementation Method 2
a 2D nanomaterial layer for patterning channels (e.g., 128) of the 2D FETs (110) between the conductive sources and the conductive drains
Implementation Method 3
a temporary etchable inert masking layer on the 2D nanomaterial layer that forms hard masked channel regions over the 2D FET channels to be patterned
Implementation Method 4
a ceramic coating layer patterned to cover portions of the chip to be electrically insulated from the liquid with openings in the ceramic coating layer corresponding to the hard masked channel regions
Data Source
AI summary
Apparatuses, systems, and methods are disclosed for an integrated circuit with 2D field-effect transistors and on-chip thin film layer deposition with electrical characterization. A corresponding layer structure and manufacturing process are disclosed. The system includes a measurement controller that determines transfer curve information and an analysis module that generates parameters for determining thickness and/or porosity and a thin film deposition controller that controllers thin film deposition using the parameters. Methods include performing liquid mediated deposition of one or more thin film layers on the channel surface and obtaining transfer curve information by generating time dependent measurement vectors for the 2D FETs and controlling and/or performing electrical characterization of the of thin film layers based on the measurement vectors. The disclosed methods may be implemented by the disclosed integrated circuit and the disclosed system.