2D FET Repeaters on Upper Metal Layers
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Solution Overview
Problem
At scaled nodes such as the 7 nm node and beyond, high via and line resistances in semiconductor devices lead to degraded chip performance, necessitating frequent insertion of repeaters which consume significant area and are degraded by high via resistances.
Innovation Solution
The use of low-temperature grown 2D transition metal dichalcogenide materials, such as MoS2, WS2, and WSe2, in upper metal routing layers to form planar FETs with reduced or no shallow trench isolation, enabling a repeater/buffer circuit with fewer Vias and improved electrostatic integrity, reducing interconnect resistance and freeing up area for other functionalities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If repeaters are inserted frequently to compensate for high via and line resistances, then chip performance is improved, but chip area is consumed significantly
Solution Approach 1:
The patent introduces an intermediate solution by forming repeater transistors directly on the upper metal routing layer using a low-temperature process that enables transistors to function as signal repeaters without requiring traditional deep substrate connections. This intermediary approach reduces via resistance while maintaining compact area through direct integration on the metal layer.
Solution Approach 2:
The patent moves the repeater transistor formation from the traditional substrate level to the upper metal routing layer, effectively changing the vertical dimension of implementation. This dimensional shift allows repeaters to be placed closer to the signal path without consuming excessive substrate area, as they utilize the metal layer space directly.
2Productivity
If metal pitch is reduced to scale interconnects, then routing density is improved, but via and line resistances increase non-linearly
Solution Approach 1:
The patent applies local quality by creating specialized repeater regions directly on upper metal layers where signal boosting is needed, rather than uniformly scaling all interconnects. The low-temperature transistor formation process enables local insertion of active repeater elements that compensate for the non-linear resistance increases in scaled metal pitches.
Solution Approach 2:
The patent changes the temperature parameter of the transistor formation process, using low-temperature deposition to create functional transistors on metal layers. This parameter change enables the creation of repeaters that can compensate for resistance issues in scaled interconnects without requiring high-temperature processing that would be incompatible with existing metal structures.
3Power
If repeaters are connected to higher metal routing layers, then signal boosting is achieved, but via resistances degrade repeater performance
Solution Approach 1:
The patent extracts the repeater transistor formation from the traditional substrate-based approach and places it directly on the upper metal routing layer. This extraction eliminates the need for multiple deep vias connecting repeaters to lower layers, thereby removing the source of high via resistance that degrades repeater performance while maintaining signal boosting capability.
4Area of stationary object
If transistors are formed on upper metal routing layers, then area is freed up, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary action by forming the repeater transistors on the metal layer during the backend processing sequence, before final packaging. The low-temperature process is integrated into the existing metal layer fabrication flow, allowing transistor formation to be prepared in advance without requiring separate high-temperature processing steps that would add significant manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces interconnect resistance, improves routing delay, and increases transistor area, leading to better chip performance by minimizing the impact of high via resistances and enabling longer gate lengths with lower leakage and reasonable threshold voltage.
Implementation Method 1
forming a crystalline material at a low temperature on the first interlayer dielectric... The crystalline material includes one or more transition metal dichalcogenide materials such as MoS2, WS2, WSe2
Data Source
AI summary
A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include one or more transition metal dichalcogenide materials such as MoS2, WS2, WSe2, and/or combinations thereof.