2D Channel FET Gate Cavity Spacer Formation Without Channel Damage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The processing of 2D materials for channel layers in field-effect transistor devices is challenging due to their delicacy, which can lead to damage during inner spacer formation, affecting yield and device performance.
Innovation Solution
A method for forming a 2D channel field-effect transistor device that involves forming a gate cavity, removing sacrificial layers, and depositing an inner spacer using an area selective deposition process, thereby avoiding direct exposure of the 2D material to spacer deposition and etch back steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional inner spacer formation techniques are used on 2D material channel layers, then the inner spacer can be formed to provide physical and electrical separation, but the 2D material channel layers are prone to damage and defect formation during inner spacer liner deposition and etch back
Solution Approach 1:
Source/drain contacts are formed prior to inner spacer formation, establishing protective structures before the delicate 2D material is exposed to potentially damaging deposition and etch processes. This preliminary action allows the inner spacer to be formed without requiring aggressive etch back steps that would damage the channel layer.
Solution Approach 2:
The method extracts or eliminates the problematic inner spacer liner etch back step from the traditional fabrication sequence. By forming the inner spacer directly without requiring liner removal, the process avoids the damaging etch exposure that would compromise the 2D material integrity.
2Ease of manufacture
If inner spacer liner deposition is performed on exposed channel layer surfaces, then the inner spacer can be formed, but defects are induced in the 2D material channel layers
Solution Approach 1:
Source/drain contacts are formed in advance to provide protective coverage over the channel layer regions where inner spacer deposition will occur. This preliminary structuring allows subsequent deposition to proceed without directly exposing the 2D material to harmful precursor materials.
Solution Approach 2:
Source/drain contacts serve as intermediary protective structures between the deposition process and the 2D material channel layer. These contacts act as a barrier that prevents direct interaction between the deposition environment and the sensitive 2D material, eliminating defect formation.
3Ease of operation
If inner spacer liner etch back is performed to reveal source/drain contact portions, then the source/drain regions are exposed, but the 2D material is damaged and degraded
Solution Approach 1:
The harmful inner spacer liner etch back step is completely removed from the fabrication sequence. The process achieves source/drain contact exposure through alternative means that do not require aggressive etching, thereby eliminating the mechanism that would damage the 2D material.
Solution Approach 2:
Source/drain contacts are formed prior to inner spacer deposition, establishing the final contact structure before any spacer formation occurs. This preliminary contact formation eliminates the need for subsequent etch back steps to expose the contacts, as they are already in their final positions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces the risk of defect formation and damage to the 2D material channel layers, improving the yield and reliability of the 2D channel FET devices by ensuring precise and controlled formation of the inner spacer and gate stack.
Implementation Method 1
depositing an inner spacer material on interior surfaces exposed in the gate cavity using an area selective deposition process
Data Source
Figure 1~2a
Figure 2b~3
Figure 4~5
AI summary
There is provided a method for forming a 2D channel field-effect transistor device (10). The method comprising: forming a device structure (100) comprising: a device layer stack (103) comprising a channel layer (104) of a 2D material and a pair of sacrificial layers (106) of a sacrificial material, wherein the channel layer is arranged between the pair of sacrificial layers (106), source/drain contacts (134) in contact with source/drain contact portions (104) of the channel layer (104) on either side of a channel region (105), and an insulating layer (130) embedding the device layer stack (103) and the source/drain contacts (134); forming a gate cavity (142) exposing the channel layer (104) and the sacrificial layers (106) along the channel region (105); removing the sacrificial layers (106) along the channel region (105) by selectively etching the sacrificial material from the gate cavity (142), thereby extending the gate cavity (142) into the device layer stack (103) between the source/drain contacts; forming an inner spacer (150) by depositing an inner spacer material on interior surfaces exposed in the gate cavity (142) using an area selective deposition process, wherein surface portions (104b) of the channel layer (104) exposed in the gate cavity (142) define deposition-inhibiting areas for the selective deposition process; and forming a gate stack (160) in the gate cavity (142), the gate stack (160) surrounding the channel layer (104) along the channel region (105) and comprising a gate dielectric (164) and one or more gate metal layers (162), wherein the gate stack (160) is laterally separated from the source/drain contacts (134) by the inner spacer (150).