2D Semiconductor Fin Channel Structure for Continued Transistor Scaling
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Solution Overview
Problem
There is a limit to reducing the size of transistors such as metal oxide semiconductor field effect transistors (MOSFETs) with a flat structure, and fin field effect transistors (FinFETs) are being studied for micro devices, but there is a need for further advancements in semiconductor devices to enhance performance and miniaturization.
Innovation Solution
The use of a two-dimensional semiconductor material as a channel layer in semiconductor devices, combined with a gate electrode having a height greater than its width, and a gate dielectric that may include high-k or ferroelectric materials, to enhance electrical properties and reduce size while maintaining high mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of transistors is reduced to enhance device density and driving speed, then productivity and performance improve, but manufacturing precision and reliability deteriorate due to size limits
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional FinFET structures by introducing vertical fins that extend from the substrate. This dimensional change allows current flow control in multiple directions (vertical and lateral), enabling continued scaling and density improvement while maintaining manufacturability through the fin geometry that provides better gate control over the channel.
Solution Approach 2:
The patent employs composite material structures including high-k dielectric materials combined with metal gate electrodes, and later integrates two-dimensional semiconductor materials like MoS2 with conventional FinFET architectures. These composite structures enable atomic-level thickness control in the channel while maintaining robust gate control and electrical performance, resolving the contradiction between miniaturization and manufacturing precision.
2Reliability
If FinFET three-dimensional structure is adopted to overcome size limits, then device performance improves, but device complexity increases
Solution Approach 1:
The patent segments the gate structure into multiple components: high-k dielectric layer, metal gate electrode, and later integrates segmented channel structures with two-dimensional materials. The source and drain regions are also segmented with selective epitaxial growth in fin regions versus planar growth in non-fin regions. This segmentation allows independent optimization of each component while managing overall device complexity.
Solution Approach 2:
The patent implements nested structures where the high-k dielectric is nested within the gate stack, which is further nested with the metal gate electrode. The two-dimensional semiconductor channel is nested within the FinFET structure, creating a multi-layer nested architecture that achieves high performance while organizing complexity in a hierarchical manner that facilitates manufacturing.
3Reliability
If channel thickness is reduced to enhance electron mobility, then electrical performance improves, but contact resistance increases
Solution Approach 1:
The patent changes the physical and chemical parameters of the channel material by introducing two-dimensional semiconductor materials with specific crystal structures (e.g., MoS2 with 1T or 2H phases). By controlling thickness at the atomic level (single-layer or few-layer) and adjusting material composition, the patent achieves high electron mobility while managing contact resistance through parameter optimization rather than simple thickness reduction.
Solution Approach 2:
The patent introduces gate dielectric intermediaries (high-k materials) between the gate electrode and the two-dimensional channel, and employs contact engineering with specific metal contacts and interface treatments. These intermediary layers and treatments mediate the interaction between electrodes and the ultra-thin channel, reducing contact resistance while preserving the high mobility benefits of atomically thin channels.
Data Source
AI summary
Provided is a semiconductor device which use a two-dimensional semiconductor material as a channel layer. The semiconductor device includes: a gate electrode on a substrate; a gate dielectric on the gate electrode; a channel layer on the gate dielectric; and a source electrode and a drain electrode that may be electrically connected to the channel layer. The gate dielectric has a shape with a height greater than a width, and the channel layer includes a two-dimensional semiconductor material.