2D Material Fin Transistors for Dense Vertical Memory Routing
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Solution Overview
Problem
Conventional vertical memory arrays face challenges in increasing memory density without compromising the overall width of the stack structure, leading to complex and congested routing paths, which impede efficient electrical connections and component integration.
Innovation Solution
The use of a microelectronic device configuration that incorporates a 2D material structure with dielectric fin structures, where the 2D material extends over and between dielectric structures, forming transistors with a folded channel configuration, allowing for increased effective channel width and improved electrical properties while maintaining a compact footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the quantity of tiers of conductive structures is increased to provide additional memory density, then memory density is improved, but routing paths become complex and congested, impeding efficient electrical connections
Solution Approach 1:
The patent transitions from planar (2D) transistor arrangements to vertical (3D) stacking architectures. By building memory arrays vertically with multiple tiers of conductive structures stacked along the vertical dimension, the design achieves higher memory density without proportionally increasing lateral routing complexity, as connections are established through vertical stacking rather than extensive lateral interconnects
2Quantity of substance
If the quantity of tiers of conductive structures is increased without increasing overall width, then memory density is improved, but conventional locations and configurations of additional components become unable to support increased quantities
Solution Approach 1:
The patent employs vertical stacking to increase memory density within a constrained lateral footprint. By arranging conductive structures and transistors in multiple vertical tiers rather than expanding laterally, the design maintains a compact overall width while accommodating increased memory capacity through the vertical dimension
Solution Approach 2:
The patent implements nested vertical stacking where multiple tiers of conductive structures are positioned one above another, with each tier containing memory cells and associated components. This nested arrangement allows higher-density integration by placing functional elements in vertical layers, enabling increased memory capacity within a compact footprint
3Ease of operation
If conventional vertical memory arrays use staircase structures for electrical connections, then electrical access is provided, but complex and congested routing paths impede desirable connection paths between components
Solution Approach 1:
The patent replaces conventional lateral staircase routing with vertical stacking architectures. Electrical connections are established through vertical interconnects between stacked tiers rather than through complex lateral staircase structures, simplifying the routing topology and reducing congestion by utilizing the vertical dimension for interconnect paths
Data Source
AI summary
A transistor comprises a 2D material structure and a gate structure. The 2D material structure conformally extends on and between surfaces of dielectric fin structures extending in parallel in a first horizontal direction, and comprises a source region, a drain region, and a channel region positioned between the source region and the drain region in the first horizontal direction. The gate structure overlies the channel region of the 2D material structure and extends in a second horizontal direction orthogonal to the first horizontal direction. The gate structure is within horizontal boundaries of the channel region of the 2D material structure in the first horizontal direction. Microelectronic devices, memory devices, and electronic systems are also described.