2D-Material GAA CFET Stacking for Sub-1 nm Transistor Scaling
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Solution Overview
Problem
Conventional semiconductor transistor technologies face challenges in scaling beyond FinFETs and nanowires, particularly in achieving further reduction to sub-nanometer sizes due to limitations in silicon-based fabrication.
Innovation Solution
The development of a complementary field effect transistor (CFET) structure using gate-all-around (GAA) configurations with transition metal dichalcogenide (TMD) channels in multiple intermetal dielectric (IMD) layers, where lower and upper GAA gate regions of opposite conductivity types are coupled with common gate voltage, enabling improved drive current and lower switching capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If silicon-based FinFET and nanowire technologies are used for transistor fabrication, then manufacturing capability is maintained, but further scaling to sub-nanometer sizes becomes problematic
Solution Approach 1:
The patent changes the material parameter from silicon to 2D materials (such as transition metal dichalcogenides), enabling continued scaling to sub-nanometer dimensions while maintaining manufacturability through alternative fabrication approaches that exploit the unique properties of 2D materials
Solution Approach 2:
The patent employs composite material structures combining 2D material channels with conventional semiconductor components (source/drain regions, gate electrodes, dielectric layers), creating a hybrid architecture that leverages both the scaling advantages of 2D materials and the成熟的 manufacturing processes of conventional semiconductors
2Use of energy by moving object
If conventional transistor structures are used, then fabrication process is simpler, but performance and energy consumption are higher
Solution Approach 1:
The patent transitions from planar (2D) transistor structures to three-dimensional gate-all-around configurations where the gate electrode completely surrounds the 2D material channel in multiple dimensions, providing superior electrostatic control and reducing leakage currents, thereby lowering energy consumption despite increased structural complexity
Solution Approach 2:
The gate electrode is nested around the 2D material channel in a gate-all-around configuration, with the gate completely enclosing the channel from all sides, maximizing the gate's control over the channel and minimizing off-state leakage, which directly reduces energy consumption
Data Source
AI summary
Disclosed is a complementary field effect transistor (CFET) formed from stacked 2D-material transistors. The 2D-material transistors are formed from transition metal dichalcogenide (TMD), which are atomically thin semiconductors. The stacked TMD transistors allow for enhanced drive current and lower switching capacitance, both of which are desirable.