2D Material Gate-All-Around Channel Structure for Short-Channel Control
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Solution Overview
Problem
As semiconductor processes become more refined, the size of transistors decreases, leading to a short channel effect characterized by threshold voltage variation, carrier velocity saturation, and degradation of subthreshold characteristics, necessitating effective measures to reduce these effects.
Innovation Solution
A semiconductor device is designed with a gate electrode that surrounds the entire surface of a channel, which includes multiple layers of two-dimensional materials, such as MoS2 or WS2, arranged in a corrugated structure to enhance electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the transistor size is decreased to increase integration density, then the degree of integration is improved, but short channel effects such as threshold voltage variation and leakage current increase
Solution Approach 1:
The gate electrode transitions from a planar structure to a three-dimensional wrap-around structure that contacts the channel from multiple directions (front, back, and sides). This dimensional change allows the gate to control the channel more effectively despite the reduced channel length, suppressing short channel effects while maintaining high integration density.
Solution Approach 2:
The gate electrode is configured to wrap around and surround the channel, with the gate insulation layer nested between them. This nested arrangement maximizes the gate's control over the channel in a compact space, enabling effective electrostatic control without increasing the device footprint.
2Use of energy by moving object
If the gate electrode and channel contact area is increased to improve power efficiency, then the power efficiency is improved, but the transistor size increases
Solution Approach 1:
The gate electrode extends to contact the channel from multiple dimensions including the front surface, back surface, and lateral sides. This multi-dimensional contact increases the effective gate-channel contact area without proportionally increasing the planar footprint, thereby improving power efficiency while maintaining compact transistor dimensions.
Solution Approach 2:
The gate electrode adopts an asymmetric wrap-around configuration that maximizes contact area with the channel in three dimensions. The gate insulation layer is selectively positioned to enable this asymmetric arrangement, allowing enhanced control and contact without symmetric expansion of the device area.
Data Source
AI summary
Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a source electrode provided on a substrate, a drain electrode disposed away from the source electrode, and a channel connected between the source electrode and the drain electrode, wherein the channel includes a plurality of first channel layers and plurality of second channel layers, and the gate electrode is provided on one surface and another surface of each of the plurality of the first channel layers and on one surface and another surface of each of the plurality of the second channel layers.