2D Semiconductor Gate Structure for Lower Contact Resistance
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Solution Overview
Problem
Semiconductor devices using two-dimensional (2D) semiconductor materials as channels face high contact resistance between the channels and metal contacts, limiting their performance due to the formation of Schottky contacts and the lack of effective current control.
Innovation Solution
The semiconductor device incorporates a unique gate structure with alternating gate lengths, allowing for both edge and top contacts between the 2D channel layers and source/drain contacts, and includes doped contact portions to reduce contact resistance, enabling improved current control and mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two-dimensional (2D) semiconductor materials are used as channels, then mobility and short channel effect suppression are improved, but contact resistance between channels and metal contacts increases
Solution Approach 1:
The gate structure is divided into multiple gate portions with alternating gate lengths (first gate portion with first gate length, second gate portion with second gate length, third gate portion with third gate length). This segmentation creates alternating edge contact and top contact regions between the source/drain contacts and the 2D channel layers, allowing optimization of contact resistance while maintaining SCE suppression.
Solution Approach 2:
Different regions of the gate structure are assigned different local properties: the first and third gate portions have longer lengths optimized for SCE suppression, while the second gate portion has a shorter length optimized for reducing contact resistance. The source/drain contacts are configured to make both edge contacts (with first gate portion) and top contacts (with second gate portion), creating locally optimized contact regions.
2Object-affected harmful factors
If alternating gate lengths are used in the gate structure, then both edge and top contacts are enabled reducing contact resistance, but device complexity increases
Solution Approach 1:
The gate structure is segmented into three distinct gate portions with alternating lengths, where the first gate portion has a first gate length, the second gate portion has a second gate length, and the third gate portion has a third gate length. This segmentation enables simultaneous formation of edge contacts (between source/drain contacts and first gate portion) and top contacts (between source/drain contacts and second gate portion), effectively reducing contact resistance while maintaining manageable structural complexity through systematic design.
Data Source
AI summary
Disclosed is a semiconductor device including a first channel layer on a substrate, and a second channel layer on the first channel layer, the first and second channel layers extending in a first direction while being spaced apart from the substrate, and including a 2D semiconductor material, a gate structure on the substrate, the gate structure extending in a second direction, and being penetrated by the first and second channel layers, and source/drain contacts on side surfaces of the gate structure and being connected to the first and second channel layers. The gate structure includes a first gate portion between the substrate and the first channel layer and having a first gate length, a second gate portion between the first and second channel layers and having a second gate length, and a third gate portion on an upper surface of the second channel layer and having a third gate length.