2D Semiconductor Gate Dielectric Stack for Uniform Deposition
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, affecting production efficiency and costs.
Innovation Solution
The method involves forming a 2-D material layer, such as a transition metal dichalcogenide monolayer, over a substrate, followed by the deposition of source/drain metals and dielectric layers using specific processes like atomic layer deposition (ALD) and physical deposition, with additional stay times and pre-oxide deposition to enhance uniformity and coverage, and forming a gate electrode and interlayer dielectric structures to improve device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency and costs are improved, but fabrication process complexity and difficulty increase
Solution Approach 1:
The fabrication process is divided into distinct stages: forming the 2-D material semiconductor layer, depositing source/drain electrodes, creating gate dielectric layers through sequential deposition, and forming gate electrodes. This segmentation allows each step to be optimized independently, managing overall process complexity while enabling continued scaling
Solution Approach 2:
The patent transitions from traditional bulk semiconductor materials to 2-D material layers (monolayer or few-layer structures), representing a dimensional change that enables continued scaling at smaller feature sizes while maintaining fabrication feasibility through unique 2-D material properties
2Productivity
If feature sizes continue to decrease to increase functional density, then chip area utilization is improved, but manufacturing reliability deteriorates
Solution Approach 1:
The patent changes the fundamental material parameter from bulk 3-D semiconductors to 2-D material layers with atomic-scale thickness, altering electrical, optical, and mechanical properties to enable reliable device operation at smaller feature sizes while maintaining or improving functional density
Solution Approach 2:
The device structure employs composite material systems including 2-D material semiconductor layers combined with conventional metals for source/drain electrodes, various dielectric materials for gate and interlayer insulation, creating a multi-material system that achieves both small feature size and high reliability
3Ease of manufacture
If conventional deposition processes are used for dielectric layers, then process simplicity is maintained, but layer uniformity and coverage deteriorate
Solution Approach 1:
A pre-oxide deposition step is performed before the main dielectric layer deposition, creating a preparatory oxide layer that improves subsequent layer uniformity and coverage. This preliminary action addresses coverage issues without requiring complete process redesign
Solution Approach 2:
The pre-oxide layer acts as an intermediary between the substrate/previous layers and the main dielectric layer, improving adhesion and uniformity of the subsequent dielectric deposition while allowing the use of standard deposition equipment and processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the uniformity and quality of dielectric layers, reduces contact resistance, and enhances device performance by increasing drain current and reducing leakage currents, thereby addressing the challenges of smaller feature sizes and complex fabrication.
Implementation Method 1
forming a first gate dielectric layer over the portion of the 2-D material semiconductor layer by using a physical deposition process; forming a second gate dielectric layer over the first gate dielectric layer by using a chemical deposition process
Implementation Method 2
forming a first gate dielectric layer over the portion of the 2-D material semiconductor layer by using a physical deposition process
Data Source
AI summary
A method includes forming a 2-D material semiconductor layer over a substrate; forming source/drain electrodes covering opposite sides of the 2-D material semiconductor layer, while leaving a portion of the 2-D material semiconductor layer exposed by the source/drain electrodes; forming a first gate dielectric layer over the portion of the 2-D material semiconductor layer by using a physical deposition process; forming a second gate dielectric layer over the first gate dielectric layer by using a chemical deposition process, in which a thickness of the first gate dielectric layer is less than a thickness of the second gate dielectric layer; and forming a gate electrode over the second gate dielectric layer.