2D Material Gate Insulator for High Mobility FETs
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Solution Overview
Problem
When two-dimensional materials are used as channels in field effect transistors, charge mobility is limited due to charge trapping at the surface of the gate insulating layer caused by dangling bonds.
Innovation Solution
A field effect transistor design incorporating a gate insulating layer made of an insulative, high-k two-dimensional material, which reduces charge trapping by eliminating dangling bonds and allowing van der Waals bonding between the gate insulating layer and the channel layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate insulating layer is used with a two-dimensional material channel, then the device structure is simple, but charge mobility is limited due to charge trapping at the interface caused by dangling bonds
Solution Approach 1:
The patent employs a composite gate insulating layer structure consisting of a first gate insulating layer and a second gate insulating layer with different dielectric constants. The first layer (higher dielectric constant) is positioned adjacent to the two-dimensional material channel, while the second layer (lower dielectric constant) is positioned away from the channel. This composite structure reduces charge trapping at the interface while maintaining electrical control, thereby improving charge mobility without excessive structural complexity.
Solution Approach 2:
The patent applies local quality by positioning the high-k dielectric material specifically at the interface region where charge trapping occurs most severely. The first gate insulating layer with higher dielectric constant is placed adjacent to the two-dimensional material channel, providing localized charge compensation and reducing interface charge density, while the second layer provides overall insulation.
2Reliability
If the gate insulating layer thickness is increased to reduce leakage, then off-current is reduced, but charge trapping at the interface increases due to dangling bonds
Solution Approach 1:
The patent uses a composite gate insulating layer where the first layer (adjacent to channel) has higher dielectric constant to reduce charge trapping, and the second layer (away from channel) provides additional thickness for leakage reduction. This composite approach simultaneously addresses both charge trapping and off-current issues.
Solution Approach 2:
The first gate insulating layer acts as an intermediary between the two-dimensional material channel and the second gate insulating layer. It provides a transition zone that reduces charge trapping at the interface while the second layer provides the necessary thickness for leakage control, thus mediating between the conflicting requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves high charge mobility and reduces off-current in the OFF state, with an interface charge density of 1×10^12 per cm^2 or less and a subthreshold swing value of about 60 mV/dec or less.
Implementation Method 1
allowing van der Waals bonding between the gate insulating layer and the channel layer
Data Source
AI summary
Provided is a field effect transistor including a gate insulating layer having a two-dimensional material. The field effect transistor may include a first channel layer; a second channel layer disposed on the first channel layer; a gate insulating layer disposed on the second channel layer; a gate electrode disposed on the gate insulating layer; a first electrode electrically connected to the first channel layer; and a second electrode electrically connected to the second channel layer. Here, the gate insulating layer may include an insulative, high-k, two-dimensional material.