2D Gate Insulating Layer for Low-Trap Field Effect Transistors
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Solution Overview
Problem
The use of two-dimensional materials as channels in field effect transistors is limited by charge trapping at the surface of the gate insulating layer due to dangling bonds, which restricts charge mobility and increases leakage current.
Innovation Solution
A field effect transistor design incorporating a gate insulating layer made of high-k, two-dimensional materials with a dielectric constant of 10 or more, such as oxide nanosheets, layered perovskites, or ferroelectric materials, which suppresses charge trapping through van der Waals bonding with the channel layer, reducing interface charge density and enhancing mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a two-dimensional material is used as a channel of a field effect transistor, then high mobility may be achieved with reduced leakage current, but the mobility of charges in the channel may be limited because charges may be trapped at a surface of a gate insulating layer due to dangling bonds
Solution Approach 1:
A two-dimensional material layer (such as h-BN, h-ALN, or h-SiN) is introduced as an intermediary between the gate insulating layer and the channel layer. This intermediate layer acts as a mediator that prevents direct interaction between charges and dangling bonds at the gate insulating layer surface, thereby reducing charge trapping while maintaining high charge mobility in the channel.
Solution Approach 2:
The gate insulating layer is constructed as a composite structure combining a three-dimensional material (such as SiO2, Si3N4, or HfO2) with a two-dimensional material layer. This composite structure leverages the high dielectric constant of the 3D material for effective gate control while the 2D material surface provides a low-trap interface, achieving both strong electrostatic control and reduced charge trapping.
2Ease of manufacture
If a conventional gate insulating layer is used, then manufacturing is simpler, but interface charge density increases due to dangling bonds
Solution Approach 1:
A two-dimensional material layer is deposited on the conventional gate insulating layer to serve as an intermediary that reduces interface charge density. This can be achieved through chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or mechanical exfoliation followed by transfer, maintaining compatibility with existing manufacturing processes while significantly reducing dangling bond effects.
Solution Approach 2:
The surface properties of the gate insulating layer are modified by changing the material phase from three-dimensional to two-dimensional. This parameter change in dimensionality fundamentally alters the surface characteristics, eliminating dangling bonds and reducing interface charge density while maintaining the electrical properties of the original gate insulating material.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves high charge mobility and reduces off-current, allowing for fast switching with a subthreshold swing value of 60 mV/dec or less, while preventing current leakage and maintaining a low interface charge density.
Implementation Method 1
suppresses charge trapping through van der Waals bonding with the channel layer
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 2C~2D
AI summary
Provided is a field effect transistor (200) including a gate insulating layer (113) having a two-dimensional material. The field effect transistor may include a first channel layer (111); a second channel layer (112) disposed on the first channel layer; a gate insulating layer (113) disposed on the second channel layer; a gate electrode (114) disposed on the gate insulating layer; a first electrode (115) electrically connected to the first channel layer (111); and a second electrode (116) electrically connected to the second channel layer (112). Here, the gate insulating layer (113) may include an insulative, high-k, two-dimensional material.