Semiconductor package and method of fabricating the same
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor devices using two-dimensional (2D) semiconductor materials as channels face high contact resistance between the channels and metal contacts, limiting their performance due to the formation of Schottky contacts and the lack of effective current control.
Innovation Solution
The semiconductor device design incorporates alternating gate lengths for channel layers, allowing for both edge and top contacts with source/drain contacts, and includes doped contact portions to reduce contact resistance, along with a method of fabricating the device using sacrificial layers and a replacement gate process to form a gate structure with specific gate lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If 2D semiconductor material is used as channel, then mobility and short channel effect are improved, but contact resistance between channel and metal contacts increases
Solution Approach 1:
The gate structure is divided into multiple gate portions with different gate lengths (first gate portion with longer gate length, second gate portion with shorter gate length) that are positioned at different locations relative to the channel layer. This segmentation allows different regions of the channel to have optimized contact configurations, with longer gate portions providing better contact resistance control and shorter gate portions enabling effective current control
Solution Approach 2:
Different gate portions are designed with different gate lengths to provide locally optimized functionality. The first gate portion with longer gate length is positioned to reduce contact resistance at specific contact regions, while the second gate portion with shorter gate length is positioned to provide effective current control at other regions, creating non-uniform local properties throughout the device
2Reliability
If gate length is increased to control short channel effect, then current control capability is improved, but device scaling is limited
Solution Approach 1:
The gate is segmented into multiple portions with different lengths positioned at different locations. The longer gate portions provide the necessary current control capability to suppress short channel effects, while the shorter gate portions allow the device to maintain smaller overall dimensions for scaling purposes
Solution Approach 2:
Instead of uniformly increasing gate length in one dimension, the invention uses multiple gate portions with different lengths arranged in a multi-dimensional configuration around the channel layer, allowing current control functionality to be distributed across different spatial locations rather than requiring a single long gate
3Reliability
If multi-gate transistor with 3D channel is used, then current control and short channel effect suppression are improved, but manufacturing complexity increases
Solution Approach 1:
The gate structure with multiple gate portions of different lengths serves multiple functions simultaneously: it provides effective current control through the longer gate portions, suppresses short channel effects through the distributed gate configuration, and maintains compatibility with existing manufacturing processes by using a modular design that can be integrated into standard fabrication flows
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces contact resistance and improves the performance of semiconductor devices by enabling both edge and top contacts, enhancing current control and mobility, and addressing the short channel effect.
Implementation Method 1
both end portions of each of the first and second channel layers include contact portions, which include the 2D semiconductor material doped with impurities
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A semiconductor device includes a first channel layer (112) on a substrate (100), and a second channel layer (114) on the first channel layer, the first and second channel layers extending in a first direction (X1) while being spaced apart from the substrate, and including a 2D semiconductor material, a gate structure (GS1) on the substrate, the gate structure extending in a second direction, and being penetrated by the first and second channel layers, and source/drain contacts (160) on side surfaces of the gate structure and being connected to the first and second channel layers. The gate structure includes a first gate portion (P1) between the substrate and the first channel layer and having a first gate length (Lg1), a second gate portion (P2) between the first and second channel layers and having a second gate length (Lg2), and a third gate portion (P3) on an upper surface of the second channel layer and having a third gate length (Lg3).