2D Gate Oxide for TMD Transistors With Low-Defect Interfaces
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Solution Overview
Problem
The scaling of multi-gate transistors to sub-10 nanometer nodes is hindered by high defect density at the interface between transition metal dichalcogenide (TMD) channels and conventional gate dielectrics, leading to performance degradation due to lack of dangling bonds for improved bonding.
Innovation Solution
Implementing a two-dimensional (2D) dielectric with Van der Waals bonding on TMD channels to reduce defects, optionally supplemented by a bulk gate dielectric to further enhance performance and leakage current management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication processes are used for multi-gate transistors, then manufacturing simplicity is maintained, but defect density at the TMD channel-gate dielectric interface increases, leading to decreased transistor performance
Solution Approach 1:
A 2D dielectric material is introduced as an intermediary layer between the TMD channel and the gate dielectric. This intermediate layer forms a clean, uniform Van der Waals bond with the TMD channel, reducing defect density at the interface and improving transistor performance while enabling aggressive scaling to sub-10 nm channel lengths
Solution Approach 2:
The patent changes the dimensional parameter of the gate dielectric from conventional bulk thickness to a 2D monolayer thickness. This parameter change enables better interface quality and reduced defect density while maintaining the necessary electrical functionality for transistor operation
2Productivity
If feature dimensions are scaled down to increase device density, then chip capacity increases, but fabrication process constraints become overwhelming
Solution Approach 1:
The patent changes the gate dielectric from a bulk 3D structure to a 2D monolayer structure, enabling scaling to sub-10 nm channel lengths. This parameter change in the gate dielectric dimension allows increased device density while the 2D structure simplifies the fabrication process by eliminating the need for complex bulk gate dielectric formation
Solution Approach 2:
The patent transitions from a three-dimensional bulk gate dielectric to a two-dimensional monolayer gate dielectric. This dimensional change enables aggressive scaling to smaller feature sizes while reducing fabrication complexity, as the 2D material can be deposited conformally on the channel structure without requiring complex bulk processing
3Reliability
If bulk gate dielectric is used, then manufacturing simplicity is maintained, but leakage current increases
Solution Approach 1:
The patent changes the gate dielectric from a bulk structure to a 2D monolayer structure with optimized thickness. This parameter change reduces leakage current by improving the interface quality and reducing the dielectric constant, while the 2D structure maintains manufacturing simplicity through conformal deposition processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of 2D dielectrics with Van der Waals bonding reduces defect density and improves transistor performance, while the additional bulk gate dielectric minimizes leakage, enabling high-performance transistor devices at smaller scales.
Implementation Method 1
Implementing a two-dimensional (2D) dielectric material that forms a clean, uniform Van der Waals bond with TMD channels, reducing defects
Data Source
AI summary
Embodiments disclosed herein include transistor devices. In an embodiment, the transistor comprises a transition metal dichalcogenide (TMD) channel. In an embodiment, a two dimensional (2D) dielectric is over the TMD channel. In an embodiment, a gate metal is over the 2D dielectric.