2D Semiconductor Gate Stack Layout for Lower Interface Resistance
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Solution Overview
Problem
2D material-based semiconductor devices are prone to large interface resistance at material interfaces, such as channel-dielectric or channel-contact interfaces, leading to degraded device performance.
Innovation Solution
A semiconductor device design featuring a substrate with a gate stack, dielectric material, and 2D material extending between gate layers and through the dielectric material to source and drain contacts, allowing for adjustable layer thickness and electrical connection to minimize interface resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the 2D material is made thin between gate layers to improve scalability, then device dimension scaling is improved, but interface resistance at channel-contact interfaces increases
Solution Approach 1:
The patent applies local quality by varying the 2D material thickness at different locations: thin between gate layers for scaling, thick at contact interfaces for low resistance. This spatial variation of thickness resolves the contradiction between scaling and interface resistance.
Solution Approach 2:
The patent transitions from uniform 2D material thickness to variable thickness by adding a vertical dimension of control. The 2D material thickness becomes a third dimension that can be independently optimized at different horizontal locations, resolving the scaling-resistance tradeoff.
2Reliability
If the 2D material thickness is increased at contact interfaces to reduce resistance, then interface resistance decreases, but device scalability is limited
Solution Approach 1:
The patent makes the 2D material locally thick only at contact regions while maintaining thin thickness in channel regions between gates. This localized thickness variation reduces contact resistance without compromising device scalability.
Solution Approach 2:
The patent segments the 2D material structure into distinct regions with different thicknesses: thin regions for channel transport and thick regions for contact interfaces. This segmentation allows independent optimization of each region's function.
Data Source
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AI summary
The present disclosure relates to semiconductor devices based on a two-dimensional (2D) channel material (104). The semiconductor device comprises a substrate (101), a gate stack arranged on the substrate, a dielectric material (103) arranged on the substrate, a source contact (105) and drain contact (106) arranged on the substrate, and the 2D material. The gate stack comprises a plurality of stacked gate layers (102). The dielectric material at least partly surrounds the gate stack. The 2D material is formed between each two subsequently stacked gate layers of the gate stack, and extends in between the dielectric material. The source contact and the drain contact are respectively electrically connected to the 2D material.