2D Semiconductor Gate Stack With SAM-Assisted Oxide Formation
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Solution Overview
Problem
The challenge lies in forming a uniform and high-quality oxide layer on two-dimensional material layers used in semiconductor devices, as existing methods face limitations in scaling due to the difficulty in maintaining crystallinity and achieving low contact resistance, especially when forming electrodes on silicon, which restricts the miniaturization of semiconductor devices.
Innovation Solution
A semiconductor device structure is proposed, featuring a two-dimensional material layer with a self-assembled monolayer between the channel layer and the gate dielectric, where the self-assembled molecules are packed side-by-side and include end and head groups that chemically bond with the two-dimensional material and gate dielectric, respectively, enhancing interfacial energy and allowing for the formation of a non-porous oxide layer with improved electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon is used for channel layers and electrodes are formed with over-doping, then contact resistance is lowered, but scaling is limited due to inability to manufacture thin silicon while maintaining crystallinity
Solution Approach 1:
The patent transitions from silicon-based channel layers to two-dimensional material layers (such as MoS2, WS2, MoSe2, WSe2), fundamentally changing the material parameter to enable atomic-layer-thin channels while maintaining semiconductivity and allowing continued device scaling without compromising crystallinity or electrical properties
Solution Approach 2:
A self-assembled monolayer is introduced as an intermediary between the two-dimensional material channel layer and the gate dielectric layer. This monolayer facilitates uniform oxide layer formation, improves interfacial quality, and enables low contact resistance without requiring over-doping, thus resolving the contradiction between achieving low contact resistance and maintaining thin channel dimensions
2Manufacturing precision
If oxide layer is formed directly on two-dimensional material layer, then gate dielectric is achieved, but uniformity and electrical properties are insufficient
Solution Approach 1:
The self-assembled monolayer is formed on the two-dimensional material surface before oxide layer deposition. This preliminary action modifies the surface properties to enable uniform oxide nucleation and growth, ensuring both uniformity and high electrical properties of the final gate dielectric structure
Solution Approach 2:
The self-assembled monolayer acts as an intermediary layer between the two-dimensional material and the oxide layer, providing a controlled interface that promotes uniform oxide formation while maintaining excellent electrical characteristics, thus simultaneously achieving both uniformity and reliability
3Productivity
If device scaling is pursued to continue miniaturization, then productivity increases, but maintaining crystallinity and electrical properties becomes difficult
Solution Approach 1:
The patent adopts two-dimensional materials with atomic-layer-thin structure that inherently maintain crystallinity at ultra-thin dimensions, enabling continued device scaling while preserving the crystalline structure and associated electrical properties that are essential for device performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of a uniform, non-porous oxide layer with enhanced electrical properties, such as increased breakdown electric field and equivalent oxide thickness, facilitating the scaling of semiconductor devices while mitigating damage to the two-dimensional material layer during surface treatment.
Implementation Method 1
a self-assembled monolayer between the channel layer and the gate dielectric, the self-assembled monolayer including self-assembled molecules packed side-by-side
Implementation Method 2
each of the self-assembled molecules may include an end group covalently bonded with the two-dimensional material layer
Implementation Method 3
a water contact angle of the self-assembled monolayer may be less than a water contact angle of the two-dimensional material layer
Data Source
AI summary
A semiconductor device including a two-dimensional material is provided. The semiconductor device may include a two-dimensional material layer having semiconductor properties, a self-assembled monolayer in which self-assembled molecules are packed side-by-side, the self-assembled monolayer being arranged on the two-dimensional material layer, and an oxide layer arranged on the self-assembled monolayer.