2D Metal Dichalcogenide Gate Stacks for Ultra-Thin Semiconductor Scaling
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Solution Overview
Problem
Conventional semiconductor device scaling techniques face challenges in forming ultra-thin gate stack layers without compromising device performance, particularly due to space limitations in next-generation architectures.
Innovation Solution
The use of 2D-transition metal dichalcogenide layers as metallic work function metal layers within the gate stack, which are deposited using cyclical deposition processes such as atomic layer deposition, allowing for the formation of ultra-thin gate stacks compatible with next-generation device architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional scaling techniques are used to reduce gate stack layer thickness, then device density and integration are improved, but device performance deteriorates due to space limitations in next-generation architectures
Solution Approach 1:
The patent employs 2D-transition metal dichalcogenide layers as ultra-thin flexible films within the gate stack structure. These 2D material layers provide the necessary electrical properties while occupying minimal space, enabling continued scaling to improve device density without compromising the electrical performance required for reliable device operation in next-generation architectures
2Adaptability or versatility
If gate stack layer thickness is reduced to meet space limitations, then compatibility with next-generation architectures is improved, but layer quality and device performance worsen
Solution Approach 1:
The patent changes the material parameters by transitioning from conventional 3D materials to 2D-transition metal dichalcogenide materials. This parameter change enables the formation of high-quality ultra-thin layers with precise thickness control at the atomic level, achieving both the required architecture compatibility and manufacturing precision for next-generation devices
Solution Approach 2:
The patent replaces conventional mechanical deposition methods with atomic layer deposition (ALD) technology. This substitution enables precise atomic-level thickness control and superior layer quality in ultra-thin gate stacks, simultaneously achieving architecture compatibility and maintaining high manufacturing precision
3Length of stationary object
If ultra-thin gate stack layers are formed, then space limitations are addressed, but layer stability and metallic properties worsen
Solution Approach 1:
The patent employs composite material structures by integrating 2D-transition metal dichalcogenide layers with high-k dielectric materials in the gate stack. This composite approach provides both the ultra-thin profile needed to address space limitations and the enhanced stability of metallic properties through the synergistic combination of materials with complementary characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of ultra-thin gate stacks with stable metallic properties, maintaining device performance while addressing the stringent space limitations in next-generation semiconductor devices.
Implementation Method 1
depositing a 2D-transition metal dichalcogenide layer directly on the dielectric layer by performing one or more deposition cycles of a cyclical deposition process. In such examples, each deposition cycle of the cyclical deposition process includes providing a transition metal precursor to the reaction chamber, and providing a chalcogen precursor to the reaction chamber
Implementation Method 2
performing one or more deposition cycles of a first atomic layer deposition process to deposit a metallic 2D-transition metal dichalcogenide work function layer directly on a surface of the high-k dielectric layer
Data Source
AI summary
Methods for forming semiconductor structures including 2D-transition metal dichalcogenide layers, methods for forming gate stacks including metallic 2D-transition metal dichalcogenide layer, as well as methods for forming ternary phase 2D-transition metal dichalcogenide layer by an atomic layer deposition process (ALD) are disclosed.