2D High-k Gate Insulator for High-Mobility Field Effect Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Field effect transistors using two-dimensional materials as channels face limited charge mobility due to charge trapping at the surface of the gate insulating layer caused by dangling bonds, which restricts the performance of the device.
Innovation Solution
A field effect transistor design incorporating a gate insulating layer made of high-k, two-dimensional materials such as oxide nanosheets, layered perovskites, or ferroelectric materials with a two-dimensional crystal structure, which reduces charge trapping by eliminating dangling bonds and enhancing mobility through van der Waals bonding with the semiconductor channel layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a two-dimensional material is used as a channel of a field effect transistor, then high mobility and reduced leakage current are achieved, but charge mobility is limited due to charge trapping at the surface of the gate insulating layer caused by dangling bonds
Solution Approach 1:
The patent changes the physical and chemical parameters of the gate insulating layer by using two-dimensional materials with high dielectric constants (k≥10) and specific crystal structures. This alters the interface properties between the gate insulating layer and channel, reducing charge trapping while maintaining high charge mobility in the two-dimensional material channel.
Solution Approach 2:
The patent employs composite material structures combining two-dimensional semiconductor materials (such as MoS2, WS2, black phosphorus) with two-dimensional high-k gate insulating materials. This composite approach leverages the high mobility of the semiconductor layer while the insulating layer provides effective gate control with reduced interface charge trapping.
2Ease of manufacture
If a conventional gate insulating layer is used, then manufacturing is easier, but charge trapping occurs due to dangling bonds at the interface
Solution Approach 1:
The patent transitions from conventional three-dimensional gate insulating materials to two-dimensional high-k materials with specific crystal structures. This parameter change eliminates dangling bonds at the interface while maintaining compatibility with existing fabrication processes through techniques such as chemical vapor deposition and exfoliation methods.
3Loss of energy
If the gate insulating layer thickness is increased to reduce leakage, then off-current is reduced, but charge mobility decreases due to stronger charge trapping effects
Solution Approach 1:
The patent utilizes two-dimensional high-k gate insulating materials with dielectric constants of 10 or higher, enabling the use of thinner physical thickness while achieving equivalent or superior electrical performance. This parameter change reduces off-current through effective gate control while minimizing interface charge trapping that would otherwise limit charge mobility.
Solution Approach 2:
The patent replaces traditional thick gate insulating layer approaches with thin two-dimensional high-k material layers. The two-dimensional crystal structure provides atomically smooth interfaces that substitute for the need for thickness-based leakage reduction, thereby maintaining high charge mobility while achieving low off-current.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of high-k, two-dimensional materials in the gate insulating layer minimizes interface charge density and enables high charge mobility, reducing off-current and achieving a subthreshold swing value of 60 mV/dec or less, leading to improved switching speed and performance.
Implementation Method 1
enhancing mobility through van der Waals bonding with the semiconductor channel layers
Implementation Method 2
the insulative, high-k, a two-dimensional material may have a dielectric constant of about 10 or more
Data Source
AI summary
Provided is a field effect transistor including a gate insulating layer having a two-dimensional material. The field effect transistor may include a first channel layer; a second channel layer disposed on the first channel layer; a gate insulating layer disposed on the second channel layer; a gate electrode disposed on the gate insulating layer; a first electrode electrically connected to the first channel layer; and a second electrode electrically connected to the second channel layer. Here, the gate insulating layer may include an insulative, high-k, two-dimensional material.