2D Semiconductor High-k Stack for Low-Leakage Gate Interfaces
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Solution Overview
Problem
The existing methods for forming gate stacks with two-dimensional semiconductor/dielectric structures, such as atomic layer deposition (ALD), result in non-uniform nuclei and islands, leading to current leakage and poor electrical performance, especially as the equivalent oxide thickness (EOT) decreases.
Innovation Solution
A method involving the oxidation of a two-dimensional semiconductor material, such as Bi2O2Se, to form a high-k material layer, which improves the interface characteristics between the channel layer and the dielectric layer, and enhances the electrical performance by reducing subthreshold swing values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If atomic layer deposition (ALD) method is used to deposit dielectric directly on two-dimensional semiconductor layer, then dielectric layer can be formed, but non-uniform nuclei and islands are formed resulting in current leakage
Solution Approach 1:
The patent introduces an organic buffer layer (perylene tetracarboxylic dianhydride) as an intermediary between the two-dimensional semiconductor layer and the high-k dielectric layer. This buffer layer provides a uniform interface that prevents direct ALD deposition defects, eliminating non-uniform nuclei and islands while maintaining effective capacitive coupling for EOT scaling.
2Reliability
If buffer layer such as perylene tetracarboxylic dianhydride is introduced to overcome ALD problems, then interface characteristics are improved, but effective EOT scaling is not achieved
Solution Approach 1:
The patent employs a composite stack structure combining organic buffer layer (perylene tetracarboxylic dianhydride) with inorganic high-k dielectric material (hafnium oxide). This composite approach allows the organic layer to provide interface quality while the inorganic high-k layer provides the necessary dielectric strength for EOT scaling, achieving both interface improvement and effective thickness reduction.
3Adaptability or versatility
If equivalent oxide thickness (EOT) is reduced to improve capacitive coupling, then controllability of gate stack is improved, but current leakage occurs due to non-uniform nuclei formation
Solution Approach 1:
The organic buffer layer serves as a mediator that enables thin EOT scaling while preventing direct contact between the ALD process and the two-dimensional semiconductor layer. This intermediary layer ensures uniform dielectric formation even at reduced thicknesses, maintaining gate stack controllability without inducing current leakage from non-uniform nuclei.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed method achieves improved interface characteristics and reduced subthreshold swing values, enabling the fabrication of electronic devices with enhanced electrical characteristics and reliability, suitable for low-power applications.
Implementation Method 1
oxidizing the two-dimensional semiconductor material layer to form a high-k material layer
Data Source
AI summary
Provided is a method for manufacturing a stack structure. The method for manufacturing a stack structure includes: preparing a substrate; forming a two-dimensional semiconductor material on the substrate; and oxidizing the two-dimensional semiconductor material using oxygen plasma to form a high-k material layer including the high-k material. The stack structure manufactured through the above-described method may be easily applied to a MOS capacitor, a field effect transistor (FET), an impact ionization super-tilt switching device, a dye-sensitized solar cell, an architectural film (particularly, a film used for window coating), and the like.