2-D Material Interconnect Structure for Lower Contact Resistance
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Solution Overview
Problem
The challenge of forming reliable semiconductor devices at smaller sizes is exacerbated by the complexity of fabrication processes as feature sizes continue to decrease, making it difficult to achieve high electron mobility and reduce contact resistance in integrated circuits.
Innovation Solution
The use of van der Waals epitaxy to grow 2-D material hetero-structures, allowing for the deposition of single-crystal metal films on 2-D material surfaces, which reduces contact resistance and improves crystalline quality, thereby enhancing the performance of integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but fabrication process difficulty and reliability increase
Solution Approach 1:
The patent changes the material parameter from conventional metals to 2-D material barrier layers, which fundamentally alters the deposition process requirements and enables reliable fabrication at smaller feature sizes
Solution Approach 2:
The patent uses composite structures combining 2-D materials with metal layers to create interconnect systems that maintain reliability at reduced feature sizes while preserving production efficiency
2Ease of manufacture
If conventional metal deposition is used, then process simplicity is maintained, but contact resistance and crystalline quality deteriorate
Solution Approach 1:
The patent introduces 2-D material layers as intermediary barrier layers between the substrate and metal deposition, which mediate the deposition process to produce superior single-crystal metal films with reduced contact resistance
Solution Approach 2:
The patent changes the deposition conditions by using 2-D material surfaces as templates, which enables standard deposition processes to produce exceptional crystalline quality and low contact resistance
3Device complexity
If standard deposition processes are used, then process complexity is minimized, but electron mobility and contact resistance performance worsen
Solution Approach 1:
The patent uses 2-D material barrier layers as intermediaries that enable standard deposition processes to achieve superior electron mobility and reduced contact resistance without increasing process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of superior crystalline quality metal films on 2-D material surfaces, leading to reduced contact resistance and lower sheet resistance, which is beneficial for interconnect applications in integrated circuits.
Implementation Method 1
The use of van der Waals epitaxy to grow 2-D material hetero-structures, allowing for the deposition of single-crystal metal films on 2-D material surfaces
Data Source
AI summary
An integrated circuit includes a substrate, a transistor over the substrate, a first inter-metal dielectric (IMD) layer over the transistor, a metal via in the first IMD layer, a first 2-D material layer cupping an underside of the metal via, a second IMD layer over the metal via, a metal line in the second IMD layer, and a second 2-D material layer cupping an underside of the metal line. The second 2-D material layer span across the metal via and the first 2-D material layer.