2-D Interconnects for Integrated Circuits
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Solution Overview
Problem
Current IC fabrication techniques face limitations in reducing feature size and pitch due to photolithography tool resolution, leading to inefficiencies and increased costs in device fabrication, particularly in achieving two-dimensional interconnects within one-dimensional patterning layouts.
Innovation Solution
The method involves forming two-dimensional interconnects in integrated circuits by using self-aligned multiple patterning processes, such as self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP), which allow for reduced feature pitch and improved pattern variability, enabling connections between even and odd numbered lines in the x-direction through two-dimensional interconnects in the y-direction, perpendicular or at an angle, matching the critical dimension of the SAMP process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography tools are used for patterning, then manufacturing process is simple, but feature size and pitch cannot be reduced below resolution limits
Solution Approach 1:
The patterning process is divided into multiple sequential steps (self-aligned double patterning or self-aligned quadruple patterning), where each step creates a portion of the final pattern. This segmentation allows achieving sub-lithography-resolution features by breaking down the complex patterning task into manageable steps that work within existing tool capabilities.
Solution Approach 2:
The patent transitions from one-dimensional patterning to two-dimensional interconnect formation. By creating vertical spacers and utilizing the third dimension (vertical stacking), the process achieves reduced pitch and complex interconnect patterns that cannot be obtained through traditional planar lithography alone.
2Manufacturing precision
If alternative methods are used to increase resolution capabilities, then feature pitch can be decreased, but critical dimensions may be inadequate and fabrication costs increase
Solution Approach 1:
The self-aligned patterning process uses the previously formed structures (mandrels, spacers) to automatically define the positions of subsequent features without requiring additional alignment steps. This self-service mechanism eliminates the need for complex alignment procedures and reduces fabrication costs while maintaining high precision.
Solution Approach 2:
Mandrels and spacers are formed in advance as sacrificial or structural elements that pre-define the positions of future interconnect features. This preliminary action allows the final pattern to be transferred with high precision without requiring real-time adjustment or complex alignment during the final patterning step.
3Adaptability or versatility
If one-dimensional patterning is used, then manufacturing is straightforward, but two-dimensional interconnects cannot be achieved
Solution Approach 1:
The patent successfully implements two-dimensional interconnect patterns by adding vertical dimension through spacer formation and stacking. The spacers extend vertically from mandrels, creating multi-level interconnect structures that enable 2-D routing while maintaining compatibility with 1-D lithography tools.
Solution Approach 2:
The interconnect structure is built in nested layers: mandrels are formed first, then spacers are deposited around them, creating a nested configuration where spacers contain mandrels. This nested structure allows compact 2-D interconnect routing within the constraints of 1-D lithography capabilities.
Data Source
AI summary
Two-dimensional (2-D) interconnects in a one-dimensional (1-D) patterning layout for integrated circuits is disclosed. This disclosure provides methods of connecting even or odd numbered lines that are in the x-direction of a 1-D patterning layout through 2-D interconnects in the y-direction. Depending on device design needs, 2-D interconnects may be perpendicular or non-perpendicular to the even or odd numbered lines. The freedom of two-dimensional patterning compared to conventional self-aligned multiple patterning (SAMP) processes used in the 1-D patterning processes is provided. The two-dimensional patterning described herein provides line widths that match the critical dimensions in both x and y directions. The separation between the 1-D lines or between 2-D interconnects and the end of 1-D lines can be kept to a constant and at a minimum.