2D M0 Metal Interconnect Layout for Detour-Free Routing
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Solution Overview
Problem
The increasing complexity and miniaturization of semiconductor integrated circuits lead to challenges such as the optical proximity effect, which causes features to short to each other, and result in increased resistance and capacitance due to detours in metal patterns, impacting performance and power consumption.
Innovation Solution
The implementation of a two-dimensional I-shaped pattern in a single metal layer using the double-patterning litho-spacer-litho-etch (LSLE) process, which avoids detours and reduces resistance by allowing direct connections between metal patterns, thereby improving routing efficiency and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional one-dimensional metal patterns are used, then manufacturing process is simpler, but routing efficiency is lower and resistance is higher due to detours
Solution Approach 1:
The patent transitions from conventional one-dimensional metal patterns to two-dimensional I-shaped metal patterns. This dimensional change allows metal patterns to extend in multiple directions (first direction and second direction perpendicular to the first direction), enabling direct routing connections without detours and improving routing efficiency while maintaining manufacturing feasibility through the double-patterning LSLE process
2Area of moving object
If feature size is decreased to increase functional density, then chip area is reduced, but optical proximity effect causes features to short to each other
Solution Approach 1:
The patent applies segmentation by dividing the metal pattern formation into two separate patterning steps (first mask pattern and second mask pattern) within the double-patterning LSLE process. This segmentation allows features to be formed with sufficient separation to avoid optical proximity effects, enabling smaller chip areas while maintaining manufacturing precision and preventing feature shorts
3Reliability
If additional metal cuts and masks are used to improve routing, then routing efficiency improves, but manufacturing complexity increases
Solution Approach 1:
The patent merges routing functionality into the base level metal interconnect patterns themselves through the two-dimensional I-shaped design, rather than requiring separate additional metal cuts and masks. The I-shaped patterns with extensions in perpendicular directions provide direct routing connections as an integral part of the metal layer structure, improving routing efficiency while avoiding increased manufacturing complexity
Data Source
AI summary
A semiconductor structure includes: a first gate structure and a second gate structure extending in a first direction; a first base level metal interconnect (M0) pattern extending in a second direction perpendicular to the first direction; a second M0 pattern extending in the second direction; a third M0 pattern located between the first and second gate structures and extending in the first direction, two ends of the third M0 pattern connected to the first M0 pattern and the second M0 pattern, respectively; a fourth M0 pattern and a fifth M0 pattern located between the first and second M0 patterns and extending in the second direction. A distance between the fourth M0 pattern and the first M0 pattern in the first direction is equal to a minimum M0 pattern pitch, and a distance between the fourth M0 pattern and the second M0 pattern is equal to the minimum M0 pattern pitch.