2D Material Carrier Nanosheets for 3D GAA Transistor Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor fabrication techniques face challenges in scaling down transistors due to short-channel effects and leakage currents, as they approach physical atomic limitations, making it difficult to continue improving performance and reducing power consumption.
Innovation Solution
A transistor architecture using 2D material layers supported by semiconductor nanosheets, with a gate structure surrounding the channel region to form a gate all-around (GAA) configuration, allowing for continued performance improvement and scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional 2D fabrication techniques are used to scale down transistors, then transistor density increases, but short-channel effects and leakage currents worsen
Solution Approach 1:
The patent transitions from conventional 2D planar transistor architecture to a 3D vertical architecture by stacking multiple nanosheet layers (e.g., four nanosheets stacked vertically) to form the channel region. This dimensional change allows continued scaling and density improvement while maintaining effective gate control over the channel, thereby addressing short-channel effects that plague 2D scaling.
Solution Approach 2:
The gate structure completely surrounds the channel region formed by the stacked nanosheets, creating a gate-all-around (GAA) configuration. This nesting of the gate around the channel provides superior electrostatic control compared to partial gate coverage, effectively suppressing short-channel effects and leakage currents while enabling further scaling.
2Productivity
If transistor features are scaled down to single nanometer dimensions, then integration density improves, but leakage currents increase
Solution Approach 1:
The gate structure completely surrounds the channel region formed by the stacked nanosheets, creating a gate-all-around (GAA) configuration. This nesting of the gate around the channel provides superior electrostatic control compared to partial gate coverage, effectively suppressing short-channel effects and leakage currents while enabling further scaling.
Solution Approach 2:
The patent employs composite material structures including stacked semiconductor nanosheets (e.g., Si/SiGe alternating layers) with different material properties. The high-k dielectric gate material combined with the nanosheet channel materials enables effective control of leakage currents at scaled dimensions while maintaining high integration density.
3Power
If 3D vertical nanosheet structures are implemented, then drive strength increases, but fabrication complexity increases
Solution Approach 1:
The channel region is segmented into multiple discrete nanosheet layers (e.g., four separate Si nanosheets) stacked vertically, each contributing to the drive strength. This segmentation allows the transistor to achieve higher drive strength compared to a single thick channel while maintaining manufacturability through established thin-film deposition and etching processes.
Solution Approach 2:
The stacked nanosheet structure serves multiple functions: it provides the channel region for carrier transport, enables gate-all-around control for electrostatic management, and allows selective doping of different nanosheet layers (e.g., undoped center layers, doped outer layers) to optimize both drive strength and leakage control within a single fabrication process flow.
Data Source
AI summary
One or more 3D transistor structures that use one or more 2D materials as transistor channels along with methods for fabricating the same are disclosed. A 3D transistor can include a first carrier nanosheet at least partially surrounded by a first 2D material and a second carrier nanosheet at least partially surrounded by a second 2D material. The transistor can include a first source/drain structure in electrical contact with a first end of the first 2D material and a first end of the second 2D material. The transistor can include a second source/drain structure in electrical contact with a second end of the first 2D material and a second end of the second 2D material. The transistor can include a gate structure at least partially surrounding the first 2D material and the second 2D material.