2D Material Select Devices for Stacked Crossbar Memory
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Solution Overview
Problem
Conventional crossbar memory systems are limited by manufacturing constraints that restrict the fabrication of select devices during back-end of line (BEOL) processes, hindering the implementation of stacked configurations and limiting memory storage density per unit volume.
Innovation Solution
Implementing select devices constructed from 2D materials, such as graphene, MoO3, WO3, MoS2, MoSe2, WS2, and WSe2, which can be fabricated during BEOL processes, enabling the creation of stacked crossbar memory systems and enhancing memory storage density by utilizing van der Waals heterostructures and p-n diodes or transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional select devices (diodes/transistors) are used in crossbar memory systems, then manufacturing is limited to front-end of line processes, but this restricts the implementation of stacked configurations and reduces memory storage density per unit volume
Solution Approach 1:
The patent changes the material parameter of select devices from conventional bulk materials to 2D materials (such as MoS2, WS2, MoSe2, WSe2, graphene). This material parameter change enables fabrication during back-end of line processes and allows implementation of stacked crossbar memory configurations, thereby resolving the contradiction between manufacturing flexibility and memory storage density.
Solution Approach 2:
The patent transitions from planar (2D) crossbar memory architecture to three-dimensional stacked crossbar memory architecture by using 2D material-based select devices. This dimensional change from single-layer to multi-layer stacking enables significantly higher memory storage density per unit volume while maintaining manufacturing feasibility through back-end of line process integration.
2Reliability
If conventional silicon-based MOSFETs are used as select devices, then fabrication is possible, but short-channel effects limit device performance and scalability
Solution Approach 1:
The patent changes the physical parameter of the select device channel from conventional silicon-based bulk material to atomically thin 2D materials. This parameter change eliminates short-channel effects because the atomic-layer thickness provides superior electrostatic control, enabling reliable device performance even at extremely small channel lengths and allowing continued device scaling.
3Quantity of substance
If stacked crossbar memory systems are implemented, then memory storage density per unit volume increases, but manufacturing complexity increases
Solution Approach 1:
The patent segments the crossbar memory system into multiple identical planar sub-systems that are stacked vertically. Each sub-system contains select devices made from 2D materials that can be fabricated using back-end of line processes. This segmentation approach allows complex 3D stacked structures to be built from simpler repeating units, reducing overall manufacturing complexity while achieving high memory storage density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of 2D materials allows for the fabrication of select devices outside traditional manufacturing limitations, enabling the creation of stacked crossbar memory systems that significantly improve memory storage density per unit volume and overcome the short-channel effect limitations of conventional silicon-based MOSFETs.
Implementation Method 1
the at least one select device is a p-n diode that includes a van der Waals heterostructure and thereby includes a 2D material
Data Source
AI summary
Systems and methods in accordance with embodiments of the invention implement select devices constructed from 2D materials. In one embodiment, a crossbar memory system includes: a first set of connection lines; a second set of connection lines; and an array of memory cells, each memory cell including: a select device; and a memory device; where each memory cell is coupled to a unique combination of: at least one connection line from the first set of connection lines, and at least one connection line from the second set of connection lines; and where at least one select device includes a 2D material.