2D Material Semiconductor Device Atomic Layer Etch Precision

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Solution Overview

Problem

Conventional methods are unable to control the layer thickness and interface composition with atomic precision, making it challenging to achieve a desired interface between gate dielectric layers and ultra-thin 2D channel materials, which is crucial for future nano-electronic devices, especially for transistors with channel lengths less than 20 nm.

Innovation Solution

The method involves forming a 2D material layer over a substrate, followed by a passivation structure using atomic layer deposition (ALD) or chemical vapor deposition (CVD), and then forming isolation structures and a gate stack with high-k dielectric materials, while using atomic layer etch (ALE) to achieve the desired thickness and precision for the passivation and gate dielectric layers, ensuring a dangling-bond free interface and reduced contact resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional fabrication methods are used, then manufacturing simplicity is maintained, but manufacturing precision of layer thickness and interface composition deteriorates

Engineering Contradiction:

Improvelayer thickness controlVSAvoidfabrication process complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The fabrication process is divided into discrete atomic layers through sequential deposition and etching cycles. Each ALD cycle deposits a controlled monolayer, and ALE removes precise atomic layers, enabling atomic-scale thickness control of the passivation structure and gate dielectric layers.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The passivation structure is formed in advance with a thickness greater than the target gate dielectric thickness. Subsequent ALE processes then remove the excess material to achieve the precise final thickness, ensuring a defect-free interface is established before final patterning.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If layer thickness is reduced to suppress short channel effect, then transistor performance is improved, but manufacturing precision requirements increase

Engineering Contradiction:

Improveshort channel effect suppressionVSAvoidinterface composition control

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

A passivation structure serving as an intermediary layer is introduced between the 2D channel material and the gate dielectric. This intermediate layer is formed with atomic precision using ALD and trimmed with ALE to provide a controlled interface that enables ultra-thin body thickness while maintaining manufacturing feasibility.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The interface composition is controlled by adjusting the chemical composition and thickness of the passivation structure through ALD process parameters. The gradual transition and chemical composition control provided by this approach enable precise interface engineering for ultra-thin devices.

Inventive Principle:

Principle #35Parameter changes

3Manufacturing precision

If atomic precision is achieved through ALD and ALE, then manufacturing precision is improved, but productivity decreases

Engineering Contradiction:

Improveinterface qualityVSAvoidfabrication throughput

Core Design Contradiction:

Manufacturing precisionVSProductivity

Solution Approach 1:

The ALD and ALE processes are performed in a continuous sequence without breaking vacuum or exposing the structure to contamination. The passivation structure formation, trimming, and gate dielectric deposition proceed through continuous atomic-layer-controlled steps, maintaining both precision and process efficiency.

Inventive Principle:

Principle #20Continuity of useful action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for the fabrication of high-performance semiconductor devices with precise control over layer thickness and interface composition, effectively suppressing short-channel effects and enhancing electron mobility, thereby increasing transistor density and performance.

Implementation Method 1

forming a passivation structure with a first thickness over the channel structure, and forming isolation structures and a gate stack with high-k dielectric materials, while using atomic layer etch (ALE) to achieve the desired thickness and precision

Methodology Applied

Scientific EffectAtomic layer deposition: Chemical Vapour Deposition

Implementation Method 2

using atomic layer etch (ALE) to achieve the desired thickness and precision for the passivation and gate dielectric layers

Methodology Applied

Scientific EffectAtomic layer etch:

Implementation Method 3

followed by a passivation structure using atomic layer deposition (ALD) or chemical vapor deposition (CVD)

Methodology Applied

Scientific EffectChemical vapor deposition: Chemical Vapour Deposition

Data Source

PatentUS10516061B2Semiconductor device and manufacturing method thereof

Publication Date: 2019.12.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor device including a field effect transistor (FET) device includes a substrate and a channel structure formed of a two-dimensional (2D) material. An interfacial layer is formed on the channel structure. A gate stack including a gate electrode layer and a gate dielectric layer is formed over the interfacial layer. Source and drain contacts are formed over openings in the interfacial layer. The source and drain contacts have a side contact with the interfacial layer and a side contact and a surface contact with the channel structure.