2D Material Source/Drain Contacts for Low Resistance
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in forming reliable semiconductor devices at increasingly smaller sizes, as feature sizes decrease, making fabrication processes more difficult and complex.
Innovation Solution
The method involves forming a first 2-D material layer, such as MoS2, on a substrate, patterning it, and creating source/drain contacts with a 2-D material layer extending along the source/drain regions, which reduces contact resistance and improves device performance by using van der Waals epitaxy and specific deposition techniques to maintain the 2-D crystal structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency improves and costs decrease, but fabrication process difficulty increases and reliability decreases
Solution Approach 1:
The patent changes the material parameter from conventional 3D metals to 2D material layers, which fundamentally alters the contact interface properties. This parameter change enables reliable electrical contact at smaller feature sizes by maintaining appropriate contact resistance characteristics that conventional materials cannot achieve at scaled dimensions.
Solution Approach 2:
The patent employs composite material structures where 2D material layers are integrated with semiconductor layers to form source/drain contacts. This composite approach combines the advantages of 2D materials (atomically thin, flexible lattice matching) with conventional semiconductor fabrication processes, enabling reliable device operation at reduced feature sizes.
2Ease of manufacture
If conventional source/drain contacts are used with 2-D material semiconductors, then fabrication is simpler, but contact resistance is high and device performance is limited
Solution Approach 1:
The patent changes the physical dimension parameter from 3D bulk metals to 2D atomic layers, which fundamentally improves the contact interface with 2D material semiconductors. This dimensional parameter change reduces contact resistance by creating a matched interface that maintains electrical continuity without requiring complex fabrication processes.
Solution Approach 2:
The patent uses van der Waals epitaxy to grow 2D contact material layers that replicate the crystal structure and bonding characteristics of the underlying 2D semiconductor. This copying approach creates atomically matched interfaces that minimize contact resistance while using simple, scalable fabrication processes.
3Reliability
If 2-D material contact layers are formed using van der Waals epitaxy, then contact resistance is reduced and device performance improves, but fabrication process complexity increases
Solution Approach 1:
The patent employs self-aligned fabrication processes where the 2D contact material layers automatically position themselves at the correct locations through van der Waals epitaxial growth. This self-service approach eliminates the need for complex alignment steps and multiple lithography processes, reducing fabrication complexity while achieving low contact resistance.
Solution Approach 2:
The patent uses continuous van der Waals epitaxial growth processes to form 2D contact layers directly on the 2D semiconductor material. This continuous process maintains the integrity of the 2D crystal structure throughout fabrication, achieving low contact resistance without requiring discrete, complex processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and performance of semiconductor devices by reducing contact resistance and maintaining the 2-D crystal structure, facilitating the fabrication of smaller and more complex circuits.
Implementation Method 1
forming a source/drain contact having a 2-D material layer that extends along a source/drain region of the 2-D material semiconductor layer, wherein the 2-D material layer comprises a group-IV element
Implementation Method 2
forming a source/drain contact having a 2-D material layer that extends along a source/drain region of the 2-D material semiconductor layer, wherein the 2-D material layer comprises a group-IV element
Implementation Method 3
maintaining the 2-D crystal structure
Implementation Method 4
using van der Waals epitaxy and specific deposition techniques to maintain the 2-D crystal structure
Data Source
AI summary
A semiconductor device includes a substrate, semiconductor 2-D material layer, a conductive 2-D material layer, a gate dielectric layer, and a gate electrode. The semiconductor 2-D material layer is over the substrate. The conductive 2-D material layer extends along a source/drain region of the semiconductor 2-D material layer, in which the conductive 2-D material layer comprises a group-IV element. The gate dielectric layer extends along a channel region of the semiconductor 2-D material layer. The gate electrode is over the gate dielectric layer.