2D Material Transistors on 3D Geometries for Reduced MOL Capacitance
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Solution Overview
Problem
FinFETs face limitations in scaling due to increasing Middle-Of-Line (MOL) parasitic capacitance, fin pitch constraints from the High-K dielectric+Metal Gate (HKMG) stack, and variability in fin shape, which hinder further miniaturization and lead to performance issues.
Innovation Solution
The use of a semiconductor 2D material layer, such as graphene or MoS2, is applied conformally on a 3D structure, including ridges or tree-shaped geometries, to enhance transistor drive strength and reduce capacitance, while the HKMG stack is modified to include 2D materials for improved scaling and consistency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FinFETs are scaled down to smaller dimensions, then transistor density and integration capacity improve, but Middle-Of-Line parasitic capacitance increases and degrades performance
Solution Approach 1:
The patent transitions from planar 2D material channels to three-dimensional nanowire structures that extend vertically. This dimensional change allows the channel to wrap around the gate electrode in a gate-all-around configuration, achieving superior electrostatic control and reduced parasitic capacitance while maintaining high transistor density through vertical stacking.
Solution Approach 2:
The patent employs composite material structures combining different semiconductor materials (e.g., SiGe source/drain regions with silicon channel, or III-V materials with III-Semiconductor channels) to optimize device performance. The composite structure enables better control of carrier transport, reduced parasitic effects, and improved scalability to smaller dimensions.
2Productivity
If fin pitch is reduced to increase transistor density, then integration capacity improves, but HKMG stack thickness constraints prevent further scaling
Solution Approach 1:
The patent adopts vertical nanowire structures that extend in the third dimension, allowing multiple nanowires to be stacked vertically within a small footprint. This vertical stacking achieves high transistor density without requiring reduced fin pitch, thereby maintaining adequate HKMG stack thickness for consistent threshold voltage control.
Solution Approach 2:
The patent segments the channel into multiple discrete nanowire segments stacked vertically, each surrounded by its own gate. This segmentation allows independent optimization of each nanowire's electrostatics and enables higher density through vertical stacking while maintaining manufacturing precision for the HKMG stack.
3Ease of manufacture
If conventional FinFET structures are used, then manufacturing is well-established, but fin shape variability causes performance variations
Solution Approach 1:
The patent employs thin-film deposition techniques to create conformal nanowire structures and gate dielectric layers that precisely follow the nanowire geometry. This approach ensures uniform material thickness and consistent device characteristics, reducing variability while maintaining compatibility with existing thin-film manufacturing processes.
Solution Approach 2:
The patent uses template-guided self-assembly or epitaxial growth methods where a sacrificial template or catalyst pattern is first formed, then the nanowire structure is grown or deposited to precisely replicate the template geometry. This copying approach ensures high shape consistency and reduces variability while using well-established thin-film and etching processes.
Data Source
AI summary
Roughly described, a transistor is formed with a semiconductor 2D material layer wrapped conformally on at least part of a 3D structure. The 3D structure can be for example a ridge made of a dielectric material, or made of dielectric material alternating longitudinally with a semiconductive or conductive material. Alternatively the 3D structure can be tree-shaped. Other shapes are possible as well. Aspects also include methods for making such structures, as well as integrated circuit layouts defining such structures and methods for developing such layouts, a machine readable data storage medium storing design entries which include some which define such structures and layouts, methods for developing such design entries. Aspects further include corrugated wafers which are prepared as an intermediate product for use in fabricating integrated circuits having a semiconductor 2D material layer disposed conformally on a 3D structure.