Two-Dimensional Memory Array Bandwidth Optimization
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Solution Overview
Problem
Existing main memory systems experience reduced data bandwidth due to idle time in memory channels, particularly with higher or variable latency memory modules, which affects overall system performance.
Innovation Solution
The implementation of a two-dimensional memory array with a master memory controller and multiple memory modules allows for concurrent access across multiple memory slices, aggregating random memory requests into compound transactions to optimize bandwidth usage and manage latency variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory modules with higher latency are introduced into the main memory, then memory capacity and flexibility are improved, but data bandwidth is reduced due to increased idle time in memory channels
Solution Approach 1:
The memory channel is divided into multiple segments or lanes, allowing parallel memory transactions to occur simultaneously. The master memory controller distributes memory requests across multiple channels, enabling concurrent access to different memory modules and reducing idle time in individual channels.
Solution Approach 2:
The patent transitions from a single-dimensional sequential memory access model to a multi-dimensional parallel access model. By organizing memory modules in a two-dimensional array and enabling access along both row and column dimensions, the system achieves higher bandwidth utilization despite individual module latency variations.
2Adaptability or versatility
If memory modules with variable latency are introduced into the main memory, then adaptability is improved, but data bandwidth is reduced due to idle time waiting for memory transactions
Solution Approach 1:
The master memory controller performs preliminary actions by pre-fetching data from memory modules before it is actually requested by the processor. It anticipates future memory needs and initiates data transfer operations in advance, thereby reducing idle time when data is finally needed.
Solution Approach 2:
The system maintains continuous useful action in memory channels by overlapping memory transactions. While one memory module is being accessed, the controller simultaneously initiates transactions with other memory modules, ensuring that memory channels remain continuously productive rather than idle during latency periods.
Data Source
AI summary
In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits.