2D Material Memory Drivers With Folded Channels for Dense Routing
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Solution Overview
Problem
Conventional vertical memory arrays face challenges in increasing memory density without causing routing congestion and connection obstacles due to complex and congested routing paths as the number of tiers and staircase structures increase.
Innovation Solution
The use of two-dimensional (2D) material structures in microelectronic devices, which include channel regions and conductively doped regions, allows for a folded channel configuration in transistors, enhancing memory density while alleviating routing congestion through optimized electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the quantity of tiers of conductive structures is increased to provide additional memory density, then memory density is improved, but routing paths become complex and congested
Solution Approach 1:
The patent transitions from planar two-dimensional transistor arrangements to three-dimensional vertical memory array architectures. By stacking multiple tiers of conductive structures vertically, the invention increases memory density without proportionally increasing lateral routing complexity, as connections are established through vertical stacking rather than extensive lateral interconnects
Solution Approach 2:
The patent implements nested staircase structures where conductive contact structures are positioned within stepped configurations of conductive structures. Each staircase structure contains multiple steps with contact regions that provide hierarchical electrical access to different tiers, organizing complex connections in a compact nested arrangement that reduces routing congestion
2Quantity of substance
If the quantity of staircase structures and steps is increased to support additional tiers, then memory density is improved, but conventional locations and configurations of additional components become unable to support the increased quantity
Solution Approach 1:
The patent divides the memory array into multiple independent staircase structures, each serving specific tiers of conductive structures. This segmentation allows each staircase to be independently configured and positioned, providing flexibility in accommodating varying numbers of tiers and contact requirements without requiring complete redesign of the entire component layout
Solution Approach 2:
The patent utilizes vertical stacking to position additional components in three-dimensional space rather than being constrained to conventional planar locations. By arranging staircase structures and contact regions in vertical layers, the invention provides adaptability for increased component quantities without expanding lateral footprint, enabling support for higher memory density configurations
Data Source
AI summary
A transistor comprises a 2D material structure and a gate structure. The 2D material structure conformally extends on and between surfaces of dielectric fin structures extending in parallel in a first horizontal direction, and comprises a source region, a drain region, and a channel region positioned between the source region and the drain region in the first horizontal direction. The gate structure overlies the channel region of the 2D material structure and extends in a second horizontal direction orthogonal to the first horizontal direction. The gate structure is within horizontal boundaries of the channel region of the 2D material structure in the first horizontal direction. Microelectronic devices, memory devices, and electronic systems are also described.