2D Metal Connection with EUV Lithography and Cut
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Solution Overview
Problem
Current semiconductor fabrication techniques face challenges in achieving high connector density and flexible via placement due to limitations in metal pitch and mask usage, particularly with one-dimensional metal connections, which result in large cell areas and increased costs with multiple patterning processes.
Innovation Solution
The use of extreme ultraviolet (EUV) lithography to pattern conductive interconnection layers and perform metal cuts, allowing for the creation of smaller, more densely spaced metal connector sections on a single semiconductor layer, enabling flexible via placement and reduced mask usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If one-dimensional metal connection process is used, then the process is simple and cell area is small, but connector density is limited and two metal layers are required
Solution Approach 1:
The patent transitions from one-dimensional metal connections (requiring two separate metal layers for X-Y routing) to two-dimensional metal connections on a single layer. This dimensional change allows connectors to be placed at any desired location within the metal layer, achieving high connector density without increasing the number of metal layers, thus resolving the contradiction between process simplicity and connector density.
2Adaptability or versatility
If two-dimensional metal shapes are patterned separately, then via placement flexibility is improved, but achievable connector density is limited and mask space is large
Solution Approach 1:
The patent merges multiple separately patterned two-dimensional metal shapes into a single monolithic metal connection structure formed by one patterning process. This consolidation maintains via placement flexibility while achieving higher connector density and reducing the required mask space, as all connectors are defined in a single exposure step rather than multiple separate patterning operations.
Solution Approach 2:
The patent uses two-dimensional metal connection geometry to enable flexible via placement at any location within the metal layer, while the single-layer implementation (rather than multiple layers) achieves higher effective connector density. The dimensional approach allows connectors to be distributed throughout the available area without the constraints of layer stacking.
3Manufacturing precision
If multiple patterning lithography is used, then smaller metal pitch is achieved, but cost increases and overlay issues occur
Solution Approach 1:
The patent employs two-dimensional metal connection patterns that can be formed using single or double patterning EUV lithography, eliminating the need for multiple patterning processes. The two-dimensional geometry allows all metal features to be defined in one or two exposures, achieving the required small metal pitch without the increased cost and overlay issues associated with multiple patterning lithography.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher connector density and more efficient via placement, reducing the need for multiple patterning and mask usage, while maintaining high resolution and critical dimension uniformity, thus improving the cost-effectiveness and performance of semiconductor fabrication.
Implementation Method 1
EUV lithography or other advanced lithography techniques may be used to achieve smaller metal pitch. Compared to other light sources commonly used for photolithography, EUV employs a shorter wavelength which can provide higher resolution and better critical dimension uniformity (CDU).
Data Source
AI summary
Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.