2D Semiconductor Nanosheet Stacks for Gate Isolation and Scaling
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Solution Overview
Problem
Current semiconductor technologies face challenges in further scaling down the size of field-effect transistors (FETs) beyond atomic level scaling, particularly in achieving effective control over nanosheet channels and ensuring adequate isolation between gate structures and source/drain regions.
Innovation Solution
The formation of a stacked structure comprising gate structures alternately stacked with dielectric layers and two-dimensional semiconductor material layers, where the gate dielectric layers contact the semiconductor material layers, and source/drain regions are formed with a different material, with spacers on the sides of the gate structures to enhance isolation and control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional FET scaling is continued, then device size reduction is achieved, but control over nanosheet channels and isolation between gate structures deteriorates
Solution Approach 1:
The patent transitions from planar FET architecture to a vertically stacked nanosheet architecture. Multiple nanosheet channels are stacked in the vertical dimension, allowing the gate to control channels from multiple directions (top, bottom, and sides). This dimensional change enables continued scaling while maintaining effective gate control and isolation, as the gate structures wrap around and contact multiple nanosheet channels in three-dimensional space rather than relying solely on planar geometry.
2Length of moving object
If atomic level scaling is pursued, then miniaturization is achieved, but manufacturing precision and structural control become difficult
Solution Approach 1:
The patent segments the channel region into multiple discrete nanosheet layers stacked vertically. Each nanosheet is a thin, two-dimensional semiconductor layer that can be independently formed and controlled. This segmentation allows the channel to be constructed from multiple manageable layers rather than attempting to scale a single continuous channel to atomic dimensions, thereby maintaining manufacturing precision while achieving miniaturization.
Solution Approach 2:
The patent employs composite material structures consisting of alternating layers of semiconductor nanosheets and dielectric materials. This composite architecture provides both mechanical support and electrical isolation, enabling precise structural control at scaled dimensions. The dielectric layers between nanosheets provide structural definition and electrical separation, making the overall structure more controllable during manufacturing while achieving atomic-level scaling.
3Area of moving object
If gate structures are scaled down, then device size is reduced, but isolation between gate structures and source/drain regions becomes inadequate
Solution Approach 1:
The gate structures are configured to wrap around and enclose the nanosheet channels in a nested arrangement. The gate dielectric and gate electrode layers surround the nanosheet channels from multiple directions, creating a nested configuration where the gate is embedded within the channel structure. This nested geometry provides effective isolation and control, as the gate structures are intimately positioned around the channels without requiring large lateral spacing, thereby maintaining isolation while reducing overall device footprint.
Data Source
AI summary
A semiconductor device comprises a stacked structure comprising a plurality of gate structures alternately stacked with a plurality of dielectric layers. Respective ones of the plurality of gate structures comprise a gate region and a gate dielectric layer disposed around the gate region. Respective ones of the plurality of dielectric layers are disposed between a first two-dimensional semiconductor material layer of a plurality of two-dimensional semiconductor material layers and a second two-dimensional semiconductor material layer of the plurality of two-dimensional semiconductor material layers. The gate dielectric layer of the respective ones of the plurality of gate structures contacts at least one of the plurality of two-dimensional semiconductor material layers.