2D Material Nanosheet Channels for High-Current Scaled Transistors
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high drive current at reduced minimum feature sizes due to the mobility constraints of conventional semiconductor materials used in nanosheet channels, limiting the integration density of electronic components.
Innovation Solution
The use of two-dimensional (2D) material nanosheets as channels in transistors, formed by alternately depositing sacrificial layers and channel stacks, which include a 2D material layer sandwiched between interfacial and high-k dielectric layers, enables higher mobility and smaller dimensions for achieving the same drive current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional semiconductor materials are used in nanosheet channels, then manufacturing process is well-established, but drive current is insufficient at reduced minimum feature sizes
Solution Approach 1:
The patent changes the material parameter from conventional semiconductor materials to two-dimensional materials (such as MoS2, WS2, WSe2, MoTe2, or h-BN), which possess inherently higher carrier mobility. This material substitution enables achieving high drive current at smaller minimum feature sizes by exploiting the superior electrical transport properties of 2D materials, directly resolving the contradiction between maintaining drive current and reducing feature size.
2Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated, but drive current becomes difficult to achieve
Solution Approach 1:
By transitioning to two-dimensional materials with higher mobility, the patent enables continued scaling to smaller feature sizes while maintaining adequate drive current. This allows integration density to increase without sacrificing the electrical performance needed for functional transistors, thus resolving the contradiction between integration density and drive current.
3Power
If two-dimensional material nanosheets are used, then higher mobility and smaller dimensions are achieved, but device structure becomes more complex
Solution Approach 1:
The patent employs a nested structure where the two-dimensional material nanosheet is sandwiched between source/drain regions and gate electrodes, with interfacial layers and dielectric layers forming concentric functional zones. This nested arrangement integrates multiple functions (channel transport, electrical contact, gating control, insulation) within a compact vertical stack, achieving high drive current while managing structural complexity through systematic layering.
Solution Approach 2:
The device structure combines two-dimensional materials with conventional semiconductor processing materials (source/drain metals, gate dielectrics, interfacial layers) to create a composite structure that leverages the high mobility of 2D materials while maintaining compatibility with existing manufacturing processes. This composite approach enables performance improvement without proportionally increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the achievement of high drive current at smaller dimensions, enabling the scaling down of semiconductor devices and balancing drive currents in n-type and p-type devices without increasing device footprint.
Implementation Method 1
formed by alternately depositing sacrificial layers and channel stacks, which include a 2D material layer sandwiched between interfacial and high-k dielectric layers
Data Source
AI summary
According to embodiments of the present disclosure, two-dimensional (2D) materials may be used as nanosheet channels for multi-channel transistors. Nanosheet channels made two-dimensional (2D) materials can achieve the same drive current at smaller dimensions and/or fewer number of channels, therefore enable scaling down and/or boost derive current. Embodiments of the present disclosure also provide a solution of P-type and N-type balancing in a device without increasing footprint of the device.