2D Nanowire Gate Spacers for Short-Channel FET Scaling
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Solution Overview
Problem
The challenge of maintaining mobility improvement and short channel control in microelectronic devices as device dimensions scale below the 10 nanometer node is exacerbated by the trade-off between critical dimension and spacing constraints in multi-gate and nanowire transistors, particularly in conventional lithographic processes.
Innovation Solution
The implementation of relatively larger internal gate spacers with a recessed 2D channel material using an isotropic etch process, combined with an isotropic etch for 2D channel materials, to balance yield and device performance, and the use of ALD metal contacts to reduce total resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional lithographic processes are used to pattern multi-gate and nanowire transistors, then manufacturing process simplicity is maintained, but the trade-off between critical dimension and spacing constraints deteriorates device performance
Solution Approach 1:
The transistor structure is segmented into multiple components: the channel region, source/drain regions, and gate electrodes positioned on different sides of the channel. This segmentation allows each region to be optimized independently for its specific function while maintaining overall device performance through the multi-gate configuration
Solution Approach 2:
The invention transitions from planar 2D channel structures to three-dimensional multi-gate and nanowire configurations. By adding vertical dimensionality with gates wrapping around the channel from multiple sides, the device achieves improved electrostatic control and carrier mobility without requiring proportionally smaller lateral dimensions, thus resolving the scaling trade-off
2Productivity
If device dimensions are scaled below the 10 nanometer node to increase functional unit density, then chip capacity increases, but maintaining mobility improvement and short channel control becomes increasingly difficult
Solution Approach 1:
The invention employs composite material structures including high-k dielectric materials combined with metal gate electrodes, and multi-layer channel structures such as nanowires and multi-gate configurations. These composite structures enable enhanced electrostatic control at sub-10nm dimensions while maintaining carrier mobility through carefully selected material properties and interfaces
3Quantity of substance
If device dimensions are reduced to increase the number of fundamental building blocks per region, then chip density increases, but spacing constraints between features worsen lithographic patterning challenges
Solution Approach 1:
By moving from two-dimensional planar transistors to three-dimensional multi-gate and nanowire structures, the invention achieves higher device density through vertical stacking and multi-sided gate configurations. This dimensional transition allows more devices to be packed into a given footprint without proportionally reducing the lateral pitch, thereby easing lithographic patterning constraints
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves yield and performance by reducing shorting issues and gate-to-contact leakage, while maintaining low total resistance and enhancing the overall performance of 2D stacking nanoribbon FETs.
Implementation Method 1
The implementation of relatively larger internal gate spacers with a recessed 2D channel material using an isotropic etch process
Implementation Method 2
the use of ALD metal contacts to reduce total resistance
Data Source
AI summary
Integrated circuit structures having internal spacers for 2D channel materials, and methods of fabricating integrated circuit structures having internal spacers for 2D channel materials, are described. For example, an integrated circuit structure includes a stack of two-dimensional (2D) material nanowires. A gate structure is vertically around the stack of 2D material nanowires. Internal gate spacers are between vertically adjacent ones of the stack of 2D material nanowires and laterally adjacent to the gate structure. The 2D material nanowires are recessed relative to the internal gate spacers. Conductive contact structures are at corresponding ends of the stack of 2D material nanowires, the conductive contact structures adjacent to the internal gate spacers and vertically overlapping with the internal gate spacers.