2D Semiconductor Oxide Gate Stack for Low-Leakage EOT Scaling
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Solution Overview
Problem
Existing methods for forming gate stacks with two-dimensional semiconductor/dielectric structures, such as atomic layer deposition, result in non-uniform nuclei and islands, leading to current leakage and poor electrical performance, especially as the equivalent oxide thickness (EOT) decreases.
Innovation Solution
A stack structure is developed comprising a channel layer with a two-dimensional semiconductor material, such as Bi2O2Se, and a dielectric layer formed by oxidizing the semiconductor material to create a high-k material layer, thereby improving interface characteristics and reducing current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If atomic layer deposition (ALD) method is used to deposit dielectric directly on two-dimensional semiconductor layer, then dielectric layer can be formed, but non-uniform nuclei and islands are formed resulting in current leakage
Solution Approach 1:
The patent introduces an organic buffer layer (perylenetetracarboxylic dianhydride) as an intermediary between the two-dimensional semiconductor layer and the high-k dielectric layer. This buffer layer mediates the interface interaction, preventing direct ALD deposition defects while maintaining effective capacitive coupling. The buffer layer acts as a mediator that resolves the contradiction between achieving uniform dielectric deposition and preventing current leakage.
Solution Approach 2:
The patent creates a composite interface structure consisting of two-dimensional semiconductor layer + organic buffer layer + high-k dielectric layer. This composite structure combines the advantages of each material: the two-dimensional semiconductor provides high charge mobility, the organic buffer layer provides uniform nucleation and prevents islands formation, and the high-k dielectric provides efficient capacitive coupling with thin equivalent oxide thickness.
2Reliability
If buffer layer is introduced to overcome ALD method problems, then current leakage is reduced, but effective EOT scaling is not achieved
Solution Approach 1:
The patent optimizes the parameters of the organic buffer layer, specifically choosing perylenetetracarboxylic dianhydride with appropriate molecular structure and thickness. This parameter optimization allows the buffer layer to be thin enough to permit effective EOT scaling while still providing sufficient coverage to prevent current leakage through uniform nucleation promotion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed stack structure achieves improved interface characteristics between the channel and dielectric layers, resulting in a subthreshold swing value close to the Boltzmann limit at room temperature, enabling low-power device operation.
Implementation Method 1
oxidizing the two-dimensional semiconductor material layer to form a high-k material layer
Data Source
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AI summary
Provided is a method for manufacturing a stack structure. The method for manufacturing a stack structure includes: preparing a substrate; forming a two-dimensional semiconductor material on the substrate; and oxidizing the two-dimensional semiconductor material using oxygen plasma to form a high-k material layer including the high-k material. The stack structure manufactured through the above-described method may be easily applied to a MOS capacitor, a field effect transistor (FET), an impact ionization super-tilt switching device, a dye-sensitized solar cell, an architectural film (particularly, a film used for window coating), and the like.