Two-Dimensional Parity Memory Error Correction
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Solution Overview
Problem
Memory elements in critical applications are increasingly susceptible to radiation-induced errors due to cosmic radiation, leading to potential system malfunctions, and existing protection methods are inefficient in reducing such errors while increasing overhead and circuit complexity.
Innovation Solution
Implementing a two-dimensional parity system with one bit of parallel and one bit of serially generated parity per memory line, reducing the overhead and logic required for error correction, and protecting critical program memory with minimal additional circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional one-dimensional Hamming codes are used for memory protection, then error detection and correction capability is improved, but overhead and circuit complexity increase significantly
Solution Approach 1:
The patent transitions from traditional one-dimensional Hamming codes to a two-dimensional parity system. Memory lines are arranged in a 2D array where horizontal parity bits protect rows and vertical parity bits protect columns. This dimensional transformation reduces the number of parity bits required while maintaining error detection and correction capabilities, thereby reducing circuit complexity and overhead.
Solution Approach 2:
The patent divides the memory protection function into two independent parity generation paths: horizontal parity generation for rows and vertical parity generation for columns. Each dimension operates independently with its own parity bits, allowing the system to detect and correct errors with fewer total parity bits compared to traditional one-dimensional approaches, thus reducing overall circuit complexity.
2Reliability
If traditional one-dimensional Hamming codes are used for memory protection, then error detection and correction capability is improved, but overhead increases
Solution Approach 1:
By organizing memory into a two-dimensional array and implementing parity bits along both horizontal and vertical dimensions, the patent reduces the total number of parity bits required. For example, in a 256-bit memory line organized as an 8x32 array, the 2D parity system requires fewer overhead bits compared to traditional 1D Hamming codes while providing equivalent or superior error protection.
3Reliability
If memory size is increased to improve error protection, then reliability is improved, but the cost and circuit size increase
Solution Approach 1:
The two-dimensional parity organization allows efficient use of memory space by arranging bits in rows and columns with shared parity structures. This reduces the total overhead required for error protection compared to traditional one-dimensional approaches, thereby reducing the overall circuit area while maintaining or improving error protection capability.
Data Source
AI summary
The parity of this invention includes two arrays of parities surrounding the memory. One array is generated in parallel. The other array is generated in serial. The two dimensional parity is used to protect, locate and correct errors automatically. The second parity is provided for only a subset of the address range of the memory. The memory controller does not compare the second parities unless there is a soft error in the first parity. The second parities are calculated upon command and not upon each memory write as the first parity.