2D Material Planar Transistor Layout for Device Scaling
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Solution Overview
Problem
There is a demand for reducing the size of semiconductor devices while improving their performance capabilities, and 2D materials offer unique properties such as high mechanical strength, electronic conductivity, and thermal conductivity, but their integration into planar transistor devices poses challenges.
Innovation Solution
The development of planar transistor devices comprising at least one layer of 2D material, with a gate structure positioned above a semiconductor substrate, featuring a channel region, source and drain regions, and 2D material layers with uniform thickness and parallel surfaces, allowing for efficient integration and performance enhancement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional semiconductor materials are used to reduce device size, then device dimensions can be scaled down, but performance capabilities deteriorate due to material limitations
Solution Approach 1:
The patent changes the material parameter from conventional bulk semiconductors to two-dimensional materials, fundamentally altering the material's dimensional characteristics and electronic properties to achieve both small size and high performance
Solution Approach 2:
The patent employs composite material structures by integrating 2D materials with conventional semiconductor substrates and device architectures, combining the advantages of both approaches
2Reliability
If 2D materials are integrated into planar transistor devices, then performance capabilities are improved through unique material properties, but integration complexity increases
Solution Approach 1:
The patent segments the transistor device into distinct functional regions with 2D materials positioned specifically in source, drain, or channel regions, allowing selective integration that manages complexity while maximizing performance benefits
Solution Approach 2:
The patent designs the 2D material integration to serve multiple functions simultaneously, including charge transport, gate control enhancement, and device scaling, thereby reducing overall system complexity despite increased material integration
3Reliability
If 2D material layers are positioned across source and drain regions, then charge carrier mobility is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies 2D materials with specific local quality characteristics to different regions (source, drain, or channel), optimizing charge carrier mobility where needed while managing manufacturing precision through region-specific integration strategies
Solution Approach 2:
The patent uses the 2D material layer as an intermediary element that bridges source and drain regions, facilitating enhanced charge carrier transport while providing a controlled interface that simplifies manufacturing precision requirements
Data Source
AI summary
A planar transistor device is disclosed including a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface, a channel region, a source region, a drain region, and at least one layer of a two-dimensional (2D) material that is positioned in at least one of the source region, the drain region or the channel region, wherein the layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the layer of 2D material in the gate length direction and across an entire width of the layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate.