2D PMOS Back-End CMOS Layers Using WSe2 and HfO2 Stacks
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Solution Overview
Problem
Current integrated circuit technologies cannot incorporate both n-channel metal-oxide semiconductor (NMOS) and p-channel metal-oxide semiconductor (PMOS) devices in back-end layers, preventing the implementation of complementary metal-oxide semiconductor (CMOS) logic circuits in these layers.
Innovation Solution
Incorporating novel transistor devices in the back-end layers of integrated circuits, including NMOS and PMOS devices, to form CMOS logic circuits, which utilize specific materials such as Indium Gallium Zinc Oxide (IGZO) and Tungsten diselenide layers with appropriate dielectric and metal layers, enabling the formation of both n-channel and p-channel transistors for CMOS logic functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If only NMOS or PMOS devices are used in back-end layers, then the manufacturing process is simpler, but CMOS logic circuits cannot be implemented
Solution Approach 1:
The patent implements CMOS logic circuits by transitioning from planar transistor structures to vertically stacked three-dimensional transistor structures in the back-end layers. This dimensional change allows both NMOS and PMOS devices to be integrated in the vertical direction, enabling CMOS functionality while maintaining compatibility with existing back-end layer manufacturing processes.
Solution Approach 2:
The patent employs composite material structures including stacked semiconductor layers with different materials (e.g., silicon-germanium, indium gallium zinc oxide, tungsten diselenide) to form both n-channel and p-channel transistors. These composite material stacks enable CMOS device formation by providing distinct material properties for electron and hole transport in the vertical channel structure.
2Adaptability or versatility
If novel transistor devices with specific materials are incorporated, then CMOS logic circuits can be formed, but the manufacturing process becomes more complex
Solution Approach 1:
The patent incorporates novel transistor devices during the back-end layer formation process itself, rather than adding them separately afterward. The stacked transistor structures are formed concurrently with the interconnect layers through integrated deposition and patterning steps, enabling CMOS logic circuit formation as part of the standard back-end manufacturing flow.
Solution Approach 2:
The stacked transistor structure serves multiple functions simultaneously: it provides both NMOS and PMOS devices for CMOS logic, forms interconnect pathways, and integrates with the back-end layer architecture. This multi-functionality reduces the need for separate manufacturing steps and simplifies the overall fabrication process despite the increased device complexity.
Data Source
AI summary
In one embodiment, a transistor device includes a metal layer, a first dielectric layer comprising Hafnium and Oxygen on the metal layer, a channel layer comprising Tungsten and Selenium above the dielectric layer, a second dielectric layer comprising Hafnium and Oxygen on the channel layer, a source region comprising metal on a first end of the channel layer, a drain region comprising metal on a second end of the channel layer opposite the first end, and a metal contact on the second dielectric layer between the source regions and the drain region. In some embodiments, the transistor device may be included in a complementary metal-oxide semiconductor (CMOS) logic circuit in the back-end of an integrated circuit device, such as a processor or system-on-chip (SoC).