Two-Dimensional Scan Architecture for Defect Diagnosis
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Solution Overview
Problem
Logic test chips with two-dimensional scan architectures are challenging to test and diagnose due to the potential defects in scan chains, which are built with logic circuit components and do not easily represent the transistor and circuit geometries of real chips, making it difficult to identify defective scan cells and interconnections.
Innovation Solution
A two-dimensional scan cell network is constructed using multiplexers to couple inputs of core scan cells to outputs of other scan cells, allowing for the creation of orthogonal and quasi-diagonal scan paths, enabling efficient identification of defective scan cells and interconnections without relying on scan patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If scan chains are built with logic circuit components to represent real chip geometries, then the test chip more closely represents real product circuits, but the testability and diagnosability of the scan chains deteriorates
Solution Approach 1:
The scan chain is segmented into multiple scan cells arranged in a two-dimensional array structure, where each scan cell can be independently accessed and tested. This segmentation allows for better diagnosability by isolating potential defects to specific regions while maintaining the logic circuit component structure that represents real chip geometries.
Solution Approach 2:
The scan chain is transformed from a traditional one-dimensional linear structure into a two-dimensional array structure. This dimensional change enables multiple scan paths (horizontal and vertical) to be formed, allowing test signals to propagate through the scan cells in different directions, thereby improving testability and diagnosability while preserving the logic circuit component representation.
2Device complexity
If traditional one-dimensional scan chains are used, then the structure is simple, but the ability to identify defective scan cells and interconnections deteriorates
Solution Approach 1:
The scan chain structure is changed from one-dimensional to two-dimensional, creating multiple scan paths (horizontal and vertical) that intersect at each scan cell. This allows defective scan cells or interconnections to be identified by analyzing which scan paths are affected, significantly improving defect detection capability while adding only moderate structural complexity.
Solution Approach 2:
Each scan cell in the two-dimensional array serves multiple functions: it can be accessed through horizontal scan paths, vertical scan paths, or both. This multi-functionality enables the same hardware structure to perform both normal operation and comprehensive testing, improving defect identification without requiring separate dedicated test structures.
3Reliability
If scan patterns are used to test logic test chips, then comprehensive coverage can be achieved, but the testing process becomes complex and time-consuming
Solution Approach 1:
The two-dimensional scan array structure enables test patterns to be applied and observed along multiple dimensions (horizontal and vertical scan paths) simultaneously. This allows for more efficient defect detection with simpler test sequences, reducing testing time while maintaining comprehensive coverage through the intersecting scan paths that can isolate and identify defective cells.
Data Source
AI summary
Aspects of the invention relate to techniques of using two-dimensional scan architecture for testing and diagnosis. A two-dimensional scan cell network may be constructed by coupling input for each scan cell to outputs for two or more other scan cells and/or primary inputs through a multiplexer. To test and diagnose the two-dimensional scan cell network, the two-dimensional scan cell network may be loaded with chain patterns and unloaded with corresponding chain test data along two or more sets of scan paths. Based on the chain test data, one or more defective scan cells or defective scan cell candidates may be determined.