2D Seed Layer Alignment for Low-Voltage Ferroelectric Transistors
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Solution Overview
Problem
Existing silicon-based electronic devices face limitations in reducing operating voltage and scaling down due to subthreshold swing limitations, leading to increased power density.
Innovation Solution
The use of a substrate with a seed layer made of two-dimensional (2D) materials and a ferroelectric layer, such as hafnium oxide or zirconium oxide, aligned within a specific crystal direction to enhance subthreshold swing characteristics, allowing for a decrease in operating voltage and improved power consumption efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If silicon-based logic transistor size is decreased, then scaling down is achieved, but operating voltage cannot be decreased to 0.8V or less due to subthreshold swing limitation
Solution Approach 1:
The patent changes the material parameter from conventional silicon-based semiconductor to ferroelectric material, which fundamentally alters the subthreshold swing characteristic. This material parameter change enables the subthreshold swing to exceed 60mV/dec, thereby allowing operating voltage to be reduced to 0.8V or less while maintaining scaled-down transistor dimensions.
Solution Approach 2:
The patent employs a composite structure combining ferroelectric material with conventional semiconductor materials. This composite approach integrates the scaling advantages of conventional transistors with the unique electrical characteristics of ferroelectric materials, achieving both small size and low operating voltage that neither material could achieve alone.
2Length of moving object
If silicon-based logic transistor size is decreased, then scaling down is achieved, but power density increases
Solution Approach 1:
By changing the material parameter to ferroelectric material, the patent achieves superior capacitance characteristics that directly reduce power consumption. The ferroelectric material's ability to maintain polarization states with minimal energy input reduces the power density penalty associated with scaled-down transistor sizes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration decreases the subthreshold swing to below 60 mV/dec, enabling reduced operating voltage and improved operational performance and efficiency in electronic devices by increasing capacitance and reducing power consumption.
Implementation Method 1
The ferroelectric layer may be configured to be aligned within a range of ±30 degrees with respect to a direction in which a (111) crystal direction is perpendicular to a top surface of the substrate
Implementation Method 2
The seed layer may have a lattice constant having a magnitude that is in a range of about 90% to about 110% with respect to a magnitude of a lattice constant of the ferroelectric layer
Data Source
AI summary
An electronic device includes a seed layer including a two-dimensional (2D) material, and a ferroelectric layer on the seed layer. The ferroelectric layer is configured to be aligned in a direction in which a (111) crystal direction is perpendicular to a top surface of a substrate on which the seed layer is located and/or a top surface of the seed layer.