2D Shift Register and Execution Lane Array for Image Processing
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Solution Overview
Problem
Traditional image processing technologies face a trade-off between versatility and power efficiency, with software-based processors consuming more energy and custom hardware processors being limited in application flexibility.
Innovation Solution
A method involving a two-dimensional shift register coupled with an execution lane array, where content is shifted and processed in parallel rows or columns, allowing for both efficient data processing and versatile application software development.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software-based processing is used on general purpose processors, then application versatility is improved, but power consumption increases
Solution Approach 1:
The processor is divided into multiple execution lanes (e.g., 16 lanes) that can be independently configured for different operations. Each lane can be programmed to perform specific tasks, allowing the system to segment workloads efficiently and reduce overall power consumption by activating only necessary lanes.
Solution Approach 2:
The execution lanes are dynamically configurable through programmable logic, allowing the processor to adapt its functionality based on workload requirements. This dynamic reconfiguration enables the system to optimize power consumption by adjusting the number and type of active execution lanes according to task complexity.
2Use of energy by moving object
If custom designed fixed function circuitry is used, then power consumption per unit of data is reduced, but application flexibility is limited
Solution Approach 1:
Each execution lane is designed as a universal processing unit capable of performing multiple operations including integer arithmetic, floating-point operations, and data shuffling. This multi-functionality allows a single hardware structure to replace multiple specialized circuits, maintaining low power consumption while providing broad application flexibility.
Solution Approach 2:
The execution lanes can change their operational parameters through programmable configuration, allowing the same hardware to adapt to different algorithms and data types. This parameter variability enables the processor to maintain efficiency across diverse applications without requiring custom hardware design for each task.
3Adaptability or versatility
If finer grained data structures with overhead are used, then programming versatility is improved, but energy consumption per unit of data increases
Solution Approach 1:
The patent extracts and eliminates unnecessary overhead operations from traditional processor architectures by implementing direct data path connections between the array structure and execution lanes. This removal of redundant instruction fetch, decode, and control overhead significantly reduces energy consumption while preserving programming versatility through the programmable execution lanes.
Data Source
AI summary
A method is described that includes loading an array of content into a two-dimensional shift register. The two-dimensional shift register is coupled to an execution lane array. The method includes repeatedly performing a first sequence including: shifting with the shift register first content residing along a particular row or column into another parallel row or column where second content resides and performing operations with a particular corresponding row or column of the execution lane array on the first and second content. The method also includes repeatedly performing a second sequence including: shifting with the shift register content from a set of first locations along a resultant row or column that is parallel with the rows or columns of the first sequence into a corresponding set of second locations along the resultant row or column. The resultant row or column has values determined from the operations of the first sequence.