2D Semiconductor Sidewall Contacts for Lower Contact Resistance
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Solution Overview
Problem
As semiconductor devices continue to reduce minimum feature sizes for increased integration density, challenges arise in forming reliable electrical contacts to two-dimensional (2D) channel layers without causing damage or contamination, leading to high contact resistance and process residue issues.
Innovation Solution
The formation of self-aligned source/drain regions that electrically contact the sidewalls of a 2D channel layer, using conductive contact layers and potentially doped Transition Metal Dichalcogenides (TMDs), reduces contact resistance and minimizes damage to the 2D material by avoiding direct contact with the planar surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional lithography processes are used to form electrical contacts to 2D channel layers, then manufacturing simplicity is maintained, but contact resistance increases and material damage occurs
Solution Approach 1:
The patent transitions from planar surface contacts to vertical sidewall contacts by forming contacts on the lateral surfaces of the gate structure. This dimensional change allows electrical contact to the 2D channel layer without requiring direct planar surface access, thereby reducing contact resistance and avoiding damage to the fragile 2D material while maintaining process feasibility through standard semiconductor fabrication techniques
2Productivity
If minimum feature sizes are reduced to increase integration density, then component integration increases, but manufacturing precision requirements worsen
Solution Approach 1:
By moving the contact formation to the vertical sidewall dimension rather than the planar surface dimension, the patent enables higher integration density without proportionally increasing manufacturing precision requirements. The sidewall contact approach utilizes the vertical space above the gate structure, effectively adding a dimensional degree of freedom that decouples integration density from lateral feature size control precision
Data Source
AI summary
A device includes a first source/drain region including: a first metal layer including a first metal; and a conductive two-dimensional material on the first metal layer; an isolation layer physically contacting a sidewall of the first metal layer, wherein the conductive two-dimensional material protrudes above the isolation layer; a two-dimensional semiconductor material on the isolation layer, wherein a sidewall of the two-dimensional semiconductor material physically contacts a sidewall of the conductive two-dimensional material; and a gate stack on the two-dimensional semiconductor material.