2D Semiconductor Sidewall Contacts for Low-Resistance Source Drain
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Solution Overview
Problem
As the minimum feature sizes in semiconductor devices are reduced, challenges arise in achieving low contact resistance between source/drain regions and two-dimensional (2D) channel layers, while also minimizing the risk of damage or contamination to the 2D channel layer.
Innovation Solution
The formation of self-aligned source/drain regions with a conductive contact layer that physically and electrically contacts the sidewalls of the 2D channel layer, using a 2D material for the contact layer and incorporating a doping layer to enhance conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional lithography and deposition processes are used to form source/drain contacts, then manufacturing process simplicity is maintained, but contact resistance increases and 2D channel layer damage risk increases
Solution Approach 1:
The method performs preliminary actions by forming the conductive contact layer conformally over the 2D channel layer before patterning, ensuring low contact resistance is achieved through pre-positioned conductive material at the contact interfaces. The doping layer is also deposited in advance to enhance conductivity before final contact formation
Solution Approach 2:
The contact structure is segmented into multiple functional layers: a 2D channel layer, a conformally deposited conductive contact layer, and an overlying doping layer. This segmentation allows each layer to perform its specific function optimally - the conductive layer provides low resistance path while the doping layer enhances carrier concentration, resolving the contradiction between low contact resistance and process simplicity
2Productivity
If feature sizes are reduced to increase integration density, then more components are integrated per area, but contact resistance increases and 2D channel layer becomes more susceptible to damage
Solution Approach 1:
The method changes the physical and chemical parameters of the contact interface by depositing a conformal conductive contact layer that adheres to the 2D channel layer surface, and introducing a doping layer to alter carrier concentration. These parameter changes enable maintenance of low contact resistance even as feature dimensions are reduced for higher integration density
Solution Approach 2:
The conductive contact layer acts as an intermediary between the 2D channel layer and subsequent metal contacts, providing a low-resistance interface that is compatible with miniaturized features. The doping layer serves as another intermediary that enhances the electrical properties of the contact region, allowing high integration density without compromising contact quality
3Ease of manufacture
If conventional contact formation methods are used, then process steps are minimized, but 2D channel layer damage or contamination occurs
Solution Approach 1:
The 2D channel layer serves itself as a template for conformal deposition of the conductive contact layer, eliminating the need for separate alignment and positioning steps. The self-aligned nature of the conformal deposition process prevents misalignment damage while the in-situ doping provides protection during subsequent processing, maintaining process simplicity without causing damage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces contact resistance, minimizes the risk of damage to the 2D channel layer, and allows for more flexible and efficient device design, improving device performance and reliability.
Implementation Method 1
incorporating a doping layer to enhance conductivity
Data Source
AI summary
A device includes a first source/drain region including: a first metal layer including a first metal; and a conductive two-dimensional material on the first metal layer; an isolation layer physically contacting a sidewall of the first metal layer, wherein the conductive two-dimensional material protrudes above the isolation layer; a two-dimensional semiconductor material on the isolation layer, wherein a sidewall of the two-dimensional semiconductor material physically contacts a sidewall of the conductive two-dimensional material; and a gate stack on the two-dimensional semiconductor material.