2D Material Stack Growth Using Crystal-Aligned Cavity Walls

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The deposition of two-dimensional materials with control over crystalline structure, morphology, and material properties remains a challenge, particularly for forming stacks of aligned layers that can outperform silicon technology in transistor scaling.

Innovation Solution

A method for forming a stack of two or more layers of two-dimensional materials, where a first layer is deposited on a flat surface with walls forming a cavity, and a second layer is grown within this cavity, ensuring alignment with the crystal structure of the first layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional deposition methods are used for two-dimensional materials, then material deposition can be achieved, but control over crystalline structure, morphology and material properties remains poor

Engineering Contradiction:
Improvecontrol over crystalline structureVSAvoiddeposition process complexity
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent changes the geometric parameters of the deposition cavity, specifically setting the aspect ratio between cavity width and height to match the crystal structure of the two-dimensional material. This parameter matching enables precise control over crystalline structure, morphology and material properties during deposition

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces a cavity structure as an intermediary element between the substrate and the two-dimensional material being deposited. This cavity acts as a template that guides crystal growth and enables control over the deposited material's properties

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If stacks of two-dimensional materials are formed to improve performance, then transistor scaling can continue, but alignment control between layers becomes increasingly difficult

Engineering Contradiction:
Improvetransistor scaling capabilityVSAvoidlayer alignment control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent performs preliminary alignment by matching the cavity's geometric parameters to the crystal structure before deposition begins. This pre-established geometric framework ensures that subsequent layers will align properly with the first layer, enabling continued transistor scaling with maintained alignment control

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses specific aspect ratios of the cavity (width-to-height ratio) that correspond to the crystal structure parameters of the two-dimensional material. This parameter matching ensures that when multiple layers are deposited, they maintain proper alignment with each other

Inventive Principle:
Principle #35Parameter changes

3Reliability

If hetero-stacks with dielectric layers are formed to improve interface properties, then interface quality can be enhanced, but device structure complexity increases

Engineering Contradiction:
Improveinterface propertiesVSAvoidhetero-stack structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by introducing dielectric layers specifically at the interfaces between two-dimensional material layers, rather than uniformly throughout the entire structure. This targeted approach enhances interface properties while minimizing overall device complexity

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method enables the precise formation of stacks with unidirectional in-plane orientation of two-dimensional materials, facilitating the fabrication of high-quality devices with improved interface properties and potential for continued transistor scaling.

Implementation Method 1

a first layer formed of a two-dimensional material in physical contact with the flat surface and with both the first and second walls at the corner, wherein the angle is adapted to align with the crystal structure of said two-dimensional materials

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentEP4535401A12d material stack formation
Publication Date: 2025.04.09 INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)
  • EP4535401A1 patent drawingFigure 1A~4B
  • EP4535401A1 patent drawingFigure 5A~8B
  • EP4535401A1 patent drawingFigure 9A~11D

AI summary

A method for forming a stack of two or more layers, the method comprising: a) providing: a flat surface (1), a first set of walls (3), comprising a first wall (31) and a second wall (32), in physical contact with the flat surface (1), and meeting at a corner (312) to form an angle, and a first layer (2) formed of a two-dimensional material in physical contact with the flat surface (1) and with both the first (31) and second walls (32) at the corner (312), wherein the angle is adapted to align with the crystal structure of said two-dimensional material with a tolerance of up to 5°, wherein a top surface (22) of the first layer (2) is exposed, wherein each of the walls (31, 32) has a length of from 5 nm to 1000 nm, wherein a height of the walls (31, 32), as measured from the exposed top surface (22) of the first layer (2) to a top (30) of the walls (31, 32), is from 0.6 nm to 2 nm, thereby forming a cavity delimited at least by the top surface (22) and the first set of walls (3), then b) forming a second layer (4, 7) in the cavity and in physical contact with the exposed top surface (22) of the first layer (2).